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MC145170

Phase–Frequency Detector PLL Frequency Synthesizer with Serial Interface

LANSDALE Semiconductor Inc. 

ML145170

LANSDALE Semiconductor, Inc.

PIN DESCRIPTIONS

DIGITAL INTERFACE PINS

Din

Serial Data Input (Pin 5)

The bit stream begins with the most significant bit (MSB)

and is shifted in on the low–to–high transition of CLK. The bit

pattern is 1 byte (8 bits) long to access the C or configuration

register, 2 bytes (16 bits) to access the N register, or 3 bytes

(24 bits) to access the R register. Additionally, the R register

can be accessed with a 15–bit transfer (see Table 1). An

optional pattern which resets the device is shown in Figure 13.

The values in the C, N, and R registers do not change during

shifting because the transfer of data to the registers is con-

trolled by ENB.

The bit stream needs neither address nor steering bits due to

the innovative BitGrabber registers. Therefore, all bits in the

stream are available to be data for the three registers. Random

access of any register is provided (i.e., the registers may be

accessed in any sequence). Data is retained in the registers

over a supply range of 2.7 to 5.5 V. The formats are shown in

Figures 13, 14, 15, and 16.

Din typically switches near 50% of VDD to maximize noise

immunity. This input can be directly interfaced to CMOS

devices with outputs guaranteed to switch near rail–to–rail.

When interfacing to NMOS or TTL devices, either a level

shifter (MC74HC14A, MC14504B) or pull–up resistor of 1 to

10 kΩ must be used. Parameters to consider when sizing the

resistor are worst–case IOL of the driving device, maximum

tolerable power consumption, and maximum data rate.

Table 1. Register Access

(MSBs are shifted in first, C0, N0, and R0 are the LSBs)

Number

of Clocks

Accessed

Register

Bit

Nomenclature

9 to 13

8

16

15 or 24

Other Values ≤ 32

Values > 32

See Figure 13

C Register

N Register

R Register

None

See Figures

24 – 31

(Reset)

C7, C6, C5,…, C0

N15, N14, N13,…, N0

R14, R13, R12,…, R0

CLK

Serial Data Clock Input (Pin 7)

Low–to–high transistion on Clock shift bits available at Din,

while high–to–low transitions shift bits from D out. The chip’s

16–1/2–stage shift register is static, allowing clock rates down

to DC in a continuous or intermittent mode.

Four to eight clock cycles followed by five clock cycles are

needed to reset the device; this is optional. Eight clock cycles

are required to access the C register. Sixteen clock cycles are

needed for the N register. Either 15 or 24 cycles can be used

to access the R register (see Table 1 and Figures 13, 14, 15,

and 16). For cascaded devices, see Figures 24 to 31.

CLK typically switches near 50% of VDD and has a

Schmitt–triggered input buffer. Slow CLK rise and fall times

are allowed. See the last paragraph of Din for more informa-

tion.

NOTE

To guarantee proper operation of the power–on reset

(POR) circuit, the CLK pin must be held at the potential

of either the VSS or VDD pin during power up. That is,

the CLK input should not be floated or toggled while

the VDD pin is ramping from 0 to at least 2.7 V. If con-

trol of the CLK pin is not practical during power up, the

initialization sequence shown in Figure 13 must be used.

ENB

Active–Low Enable Input (Pin 6)

This pin is used to activate the serial interface to allow the

transfer of data to/from the device. When ENB is in an inactive

high state, shifting is inhibited, Dout is forced to the

high–impedance state, and the port is held in the initialized

state. To transfer data to the device, ENB (which must start

inactive high) is taken low, a serial transfer is made via Din and

CLK, and ENB is taken back high. The low–to–high transition

on ENB transfers data to the C, N, or R register depending on

the data stream length per Table 1.

Note

Transitions on ENB must not be attempted while CLK

is high. This puts the device out of synchronization

with the microcontroller. Resynchronization occurs

when ENB is high and CLK is low.

This input is also Schmitt–triggered and switches near 50%

of VDD, thereby minimizing the chance of loading erroneous

data into the registers. See the last paragraph of Din for more

information.

Dout

Three–State Serial Data Output (Pin 8)

Data is transferred out of the 16–1/2–stage shift register

through Dout on the high–to–low transition of CLK. This out-

put is a No Connect, unless used in one of the manners dis-

cussed below.

Dout could be fed back to an MCU/MPU to perform a

wrap–around test of serial data. This could be part of a system

check conducted at power up to test the integrity of the sys-

tem’s processor, PC board traces, solder joints, etc.

Finally, Dout facilitates trouble shooting a system and per-

mits cascading devices.

REFERENCE PINS

OSCin/OSCout

Reference Oscillator Input/Output (Pins 1, 2)

These pins form a reference oscillator when connected to

terminals of an external parallel–resonant crystal. Frequency

setting capacitors of appropriate values as recommended by the

crystal supplier are connected from each pin to ground (up to a

maximum of 30 pF each, including stray capacitance). An

external feedback resistor of 1.0 to 5.0 MΩ is connected

directly across the pins to ensure linear operation of the ampli-

fier. The required connections for the components are shown in

Figure 9.

If desired, an external clock source can be AC coupled to

OSCin. A 0.01 µF coupling capacitor is used for measurement

purposes and is the minimum size recommended for

Page 8 of 26

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