UDA1330A 데이터 시트보기 (PDF) - Philips Electronics
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UDA1330A Datasheet PDF : 24 Pages
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Philips Semiconductors
Low-cost stereo filter DAC
Preliminary specification
UDA1330ATS
handbook, full pagewidth
L3MODE
tstp(L3)
L3CLOCK
L3DATA
address
data byte #1
data byte #2
address
MGL725
Fig.6 Multibyte data transfer.
Programming the features
When the data transfer of type ‘status’ is selected, the features for the system clock frequency and the data input format
can be controlled.
Table 6 Data transfer of type ‘status’
BIT 7
0
1
BIT 6
0
0
BIT 5
SC1
0
BIT 4
SC0
0
BIT 3
IF2
0
BIT 2
IF1
0
BIT 1
IF0
0
BIT 0
0
0
REGISTER SELECTED
SC = system clock frequency (2 bits); see Table 8
IF = data input format (3 bits); see Table 9
not used
When the data transfer of type ‘data’ is selected, the features for volume, de-emphasis and mute can be controlled.
Table 7 Data transfer of type ‘data’
BIT 7
0
0
1
1
BIT 6
0
1
0
1
BIT 5
VC5
0
0
0
BIT 4
VC4
0
DE1
0
BIT 3
VC3
0
DE0
0
BIT 2
VC2
0
MT
0
BIT 1
VC1
0
0
0
BIT 0
VC0
0
0
1
REGISTER SELECTED
VC = volume control (6 bits); see Table 11
not used
DE = de-emphasis (2 bits); see Table 10
MT = mute (1 bit); see Table 12
default setting
2000 Apr 18
10
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