ADT7468ARQZ-RL7 데이터 시트보기 (PDF) - ON Semiconductor
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ADT7468ARQZ-RL7 Datasheet PDF : 81 Pages
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If THERM is enabled (Bit 1, Configuration Register 3 at
Address 0x78):
• Pin 20 becomes THERM.
• If Pin 14 is configured as THERM (Bit 0 and Bit 1 of
Configuration Register 4 at Address 0x7D), then THERM
is enabled on this pin.
If THERM is not enabled:
• Pin 20 becomes a 5 V measurement input.
• If Pin 14 is configured as THERM, then THERM is
disabled on this Pin.
Table 13. Configuring Pin 14
Bit 0
Bit 1
Function
0
0
TACH4
0
1
THERM
1
0
SMBALERT
1
1
GPIO
THERM as an Input
When THERM is configured as an input, the user can
time assertions on the THERM pin. This can be useful for
connecting to the PROCHOT output of a CPU to gauge
system performance.
The user can also set up the ADT7468 to run the fans at 100%
whenever the THERM pin is driven low externally by setting
the boost bit (Bit 2) in Configuration Register 3 (Address 0x78)
to 1. Note that to set this up, the fan must be already running,
for example, in manual mode when the current duty cycle is
above 0x00, or in automatic mode when the temperature is
above TMIN. If the temperature is below TMIN or if the duty cycle
in manual mode is set to 0x00, then pulling the THERM low
externally has no effect. See Figure 30 for more information.
TMIN
THERM
ADT7468
THERM Timer
The ADT7468 has an internal timer to measure THERM
assertion time. The THERM input can be connected to the
PROCHOT output of a Pentium 4 CPU to measure system
performance or be connected to the output of a trip point
temperature sensor, to name a couple of functions of the timer.
The timer is started on the assertion of the ADT7468’s THERM
input and stopped when THERM is unasserted. The timer
counts THERM times cumulatively, that is, the timer resumes
counting on the next THERM assertion. The THERM timer
continues to accumulate THERM assertion times until the
timer is read (it is cleared on read) or until it reaches full scale.
If the counter reaches full scale, it stops at that reading until
cleared.
The 8-bit THERM timer register (Reg. 0x79) is designed such
that Bit 0 is set to 1 on the first THERM assertion. Once the
cumulative THERM assertion time has exceeded 45.52 ms, Bit 1
of the THERM timer is set and Bit 0 now becomes the LSB of
the timer with a resolution of 22.76 ms (see Figure 31).
When using the THERM timer, be aware of the following after a
THERM timer read (Reg. 0x79):
1. The contents of the timer are cleared on read.
2. The F4P bit (Bit 5) of Status Register 2 needs to be cleared
(assuming that the THERM timer limit has been
exceeded).
If the THERM timer is read during a THERM assertion, then
the following happens:
1. The contents of the timer are cleared.
2. Bit 0 of the THERM timer is set to 1 (because a THERM
assertion is occurring).
3. The THERM timer increments from 0.
4. If the THERM timer limit (Reg. 0x7A) = 0x00, then the
F4P bit is set.
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100%, BECAUSE
TEMPERATURE IS BELOW TMIN
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100%, BECAUSE
TEMPERATURE IS ABOVE TMIN AND FANS
ARE ALREADY RUNNING
Figure 30. Asserting THERM Low as an Input
in Automatic Fan Speed Control Mode
Rev. 3 | Page 25 of 81 | www.onsemi.com
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