24501BVA 데이터 시트보기 (PDF) - Intersil
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24501BVA Datasheet PDF : 8 Pages
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HM-6504
Timing Waveforms (Continued)
(7)
TAVEL
A
ADD VALID
E
(6)
TEHEL
W
(8)
TELAX
(18) TELEL
(5) TELEH
(10)
(9) TWLEH
TWLWH
(14)
TDVWL
(16)
TWLDX
D
DATA VALID
HIGH Z
Q
(3)
TELQX
TIME
REFERENCE
-1
0
1
2
FIGURE 13. LATE WRITE CYCLE
(7)
TAVEL
NEXT ADD
(6)
TEHEL
(4)
TEHQZ
HIGH Z
3
4
5
TRUTH TABLE
TIME
INPUTS
OUTPUTS
REFERENCE
E
W
A
D
Q
FUNCTION
-1
H
X
X
X
Z
Memory Disabled
0
H
V
X
Z
Cycle Begins, Addresses are Latched
1
L
X
V
X
Write Begins, Data is Latched
2
L
H
X
X
X
Write In Progress Internally
3
H
X
X
X
Write Completed
4
H
X
X
X
Z
Prepare for Next Cycle (Same as -1)
5
H
V
X
Z
Cycle Ends, Next Cycle Begins (Same as 0)
The late write cycle is a cross between the early write cycle
and the read-modify-write cycle.
Recall that in the early write, the output is guaranteed to
remain high impedance, and in the read-modify-write the
output is guaranteed valid at access time. The late write is
between these two cases. With this cycle the output may
become active, and may become valid data, or may remain
active but undefined. Valid data is written into the RAM if
data setup, data hold, write setup and write pulse widths are
observed.
6-132
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