BUK107-50GL 데이터 시트보기 (PDF) - Philips Electronics
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BUK107-50GL Datasheet PDF : 10 Pages
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Philips Semiconductors
PowerMOS transistor
Logic level TOPFET
Product specification
BUK107-50GL
200 Tj(TO) / C
BUK107-50GL
180
160
140
TYP.
120
100
80
60
0
2
4
6
8
10
VIS / V
Fig.8. Typical overtemperature protection threshold.
Tj(TO) = f(VIS); condition: VDS = 10 V
IIS & IISL / mA
2
BUK107-50GL
LATCHED
1
IISL
RESET
NORMAL
IIS
0
0
2
4
6
8
VIS / V
Fig.9. Typical DC input characteristics, Tj = 25 ˚C.
IIS & IISL = f(VIS); normal operation & protection latched
IIS / uA
500
400
300
VIS / V =
5V
BUK107-50GL
200
4V
100
0
-50
0
50
100
150
Tj / C
Fig.10. Typical DC input current.
IIS = f(Tj); parameter VIS; normal operation
VIS(TO) / V
3
2
1
BUK107-50GL
MAX.
TYP.
MIN.
-50
0
50
100
150
Tj / C
Fig.11. Input threshold voltage.
VIS(TO) = f(Tj); conditions: ID = 1 mA; VDS = 5 V
II / mA
10
BUK107-50GL
9
8
7
6
5
4
3
2
1
0
0
2
4
6
8
10
VIS / V
Fig.12. Typical input clamping characteristic.
II = f(VIS); normal operation, Tj = 25 ˚C.
ID / mA
200
BUK107-50GL
150
TYP.
100
50
0
50
52
54
56
58
60
VDS / V
Fig.13. Overvoltage clamping characteristic, 25 ˚C.
ID = f(VDS); conditions: VIS = 0 V; tp ≤ 300 µs
April 1998
6
Rev 1.200
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