59441IAZ 데이터 시트보기 (PDF) - Renesas Electronics
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59441IAZ Datasheet PDF : 12 Pages
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ISL59441
PC Board Layout
The frequency response of this circuit depends greatly on the
care taken in designing the PC board. The following are
recommendations to achieve optimum high frequency
performance from your PC board.
• The use of low inductance components such as chip
resistors and chip capacitors is strongly recommended.
• Minimize signal trace lengths. Trace inductance and
capacitance can easily limit circuit performance. Avoid sharp
corners, use rounded corners when possible. Vias in the
signal lines add inductance at high frequency and should be
avoided. PCB traces greater than 1" begin to exhibit
transmission line characteristics with signal rise/fall times of
1ns or less. High frequency performance may be degraded
for traces greater than one inch, unless strip lines are used.
• Match channel-channel analog I/O trace lengths and layout
symmetry. This will minimize propagation delay mismatches.
• Maximize use of AC de-coupled PCB layers. All signal I/O
lines should be routed over continuous ground planes (i.e.
no split planes or PCB gaps under these lines). Avoid vias in
the signal I/O lines.
• Use proper value and location of termination resistors.
Termination resistors should be as close to the device as
possible.
• When testing use good quality connectors and cables,
matching cable types and keeping cable lengths to a
minimum.
• Minimum of 2 power supply de-coupling capacitors are
recommended (1000pF, 0.01µF) as close to the device as
possible. Avoid vias between the cap and the device
because vias add unwanted inductance. Larger caps can be
farther away. When vias are required in a layout, they should
be routed as far away from the device as possible.
• The NIC pins are placed on both sides of the input pins.
These pins are not internally connected to the die. It is
recommended these pins be tied to ground to minimize
crosstalk.
FN6163 Rev 2.00
September 21, 2005
Page 11 of 12
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