SC28L92 데이터 시트보기 (PDF) - NXP Semiconductors.
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SC28L92 Datasheet PDF : 73 Pages
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NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
Table 2.
Symbol
GND
n.c.
Pin description for 80xxx bus interface (Intel) …continued
Pin
Type Description
PLCC44 QFP44 HVQFN48
22
16, 17 18[1]
Pwr Ground
1, 23, 34 23
6, 13, 24, 25, Pwr Not connected
36, 37, 43
[1] HVQFN48 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
Table 3. Pin description for 68xxx bus interface (Motorola)
Symbol Pin
Type Description
PLCC44 QFP44 HVQFN48
I/M
12
11
7
I
Bus configuration: When LOW configures the bus interface to the
conditions shown in this table.
D0
28
D1
18
D2
27
22
23
12
14
21
22
I/O Data bus: Bidirectional 3-state data bus used to transfer commands,
I/O data and status between the DUART and the CPU. D0 is the least
significant bit.
I/O
D3
19
13
15
I/O
D4
26
20
21
I/O
D5
20
14
16
I/O
D6
25
19
20
I/O
D7
21
15
17
I/O
CEN
39
33
35
I
Chip enable: Active LOW input signal. When LOW, data transfers
between the CPU and the DUART are enabled on D0 to D7 as
controlled by the R/WN and A0 to A3 inputs. When HIGH, places the
D0 to D7 lines in the 3-state condition.
R/WN 9
3
3
I
Read/Write: Input signal. When CEN is LOW, R/WN HIGH input
indicates a read cycle; when LOW indicates a write cycle.
IACKN 41
35
39
I
Interrupt acknowledge: Active LOW input indicating an interrupt
acknowledge cycle. Usually asserted by the CPU in response to an
interrupt request. When asserted places the interrupt vector on the
bus and asserts DACKN.
DACKN 10
4
4
O Data transfer acknowledge: A3-state active LOW output asserted in
a write, read, or interrupt acknowledge cycle to indicate proper
transfer of data between the CPU and the DUART.
A0
2
A1
4
40
44
42
46
I
Address inputs: Select the DUART internal registers and ports for
I
read/write operations.
A2
6
44
48
I
A3
7
1
1
I
RESETN 38
32
34
I
Reset: A LOW level clears internal registers (SRA, SRB, IMR, ISR,
OPR, OPCR), puts OP0 to OP7 in the HIGH state, stops the
counter/timer, and puts channels A and B in the inactive state, with the
TxDA and TxDB outputs in the mark (HIGH) state. Sets MR pointer to
MR1. See Figure 10.
SC28L92_7
Product data sheet
Rev. 07 — 19 December 2007
© NXP B.V. 2007. All rights reserved.
11 of 73
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