CS5166 데이터 시트보기 (PDF) - ON Semiconductor

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CS5166

5−Bit Synchronous CPU Controller with Power Good and Current Limit

ON Semiconductor 

CS5166

Switch on time is limited by an internal 30 μs (typical)

timer, minimizing stress to the power components.

Programmable Output

The CS5166 is designed to provide two methods for

programming the output voltage of the power supply. A five

bit on board digital to analog converter (DAC) is used to

program the output voltage within two different ranges. The

first range is 2.125 V to 3.525 V in 100 mV steps, the second

is 1.325 V to 2.075 V in 50 mV steps, depending on the

digital input code. If all five bits are left open, the CS5166

enters adjust mode. In adjust mode, the designer can choose

any output voltage by using resistor divider feedback to the

VFB pin, as in traditional controllers. The CS5166 is

specifically designed to meet or exceed Intel’s Pentium II

specifications.

Start Up

Until the voltage on the VCC supply pin exceeds the 3.95 V

monitor threshold, the Soft Start and GATE pins are held

low. The FAULT latch is reset (no Fault condition). The

output of the error amplifier (COMP) is pulled up to 1.0 V by

the comparator clamp. When the VCC pin exceeds the

monitor threshold, the GATE(H) output is activated, and the

Soft Start capacitor begins charging. The GATE(H) output

will remain on, enabling the NFET switch, until terminated

by either the PWM comparator, or the maximum on time

timer.

If the maximum on time is exceeded before the regulator

output voltage achieves the 1.0 V level, the pulse is

terminated. The GATE(H) pin drives low, and the GATE(L)

pin drives high for the duration of the extended off time. This

time is set by the time out timer and is approximately equal

to the maximum on time, resulting in a 50% duty cycle. The

GATE(L) pin will then drive low, the GATE(H) pin will

drive high, and the cycle repeats.

When regulator output voltage achieves the 1.0 V level

present at the COMP pin, regulation has been achieved and

normal off time will ensue. The PWM comparator

terminates the switch on time, with off time set by the COFF

capacitor. The V2 control loop will adjust switch duty cycle

as required to ensure the regulator output voltage tracks the

output of the error amplifier.

The Soft Start and COMP capacitors will charge to their

final levels, providing a controlled turn on of the regulator

output. Regulator turn on time is determined by the COMP

capacitor charging to its final value. Its voltage is limited by

the Soft Start COMP clamp and the voltage on the Soft Start

pin.

M 250 μs

Trace 1− Regulator Output Voltage (1.0 V/div.)

Trace 2− Inductor Switching Node (2.0 V/div.)

Trace 3− 12 V Input (VCC) (5.0 V/div.)

Trace 4− 5.0 V Input (1.0 V/div.)

Figure 11. Demonstration Board Startup in Response

to Increasing 12 V and 5.0 V Input Voltages. Extended

Off Time is Followed by Normal Off Time Operation

when Output Voltage Achieves Regulation to the Error

Amplifier Output.

Trace 1− Regulator Output Voltage (1.0 V/div.)

Trace 3− COMP PIn (error amplifier output) (1.0 V/div.)

Trace 4− Soft Start Pin (2.0 V/div.)

Figure 12. Demonstration Board Startup Waveforms

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