HI-8685 데이터 시트보기 (PDF) - Holt Integrated Circuits

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HI-8685

ARINC INTERFACE DEVICE ARINC 429 & 561 Serial Data to 16-Bit Parallel Data

Holt Integrated Circuits 

HI-8685, HI-8686

TIMING DIAGRAMS

VDIFF

RINA - RINB

ARINC Data Bits

28 29 30 31 32

Word Gap

4 Bit Periods Min.

DERIVED DATA

DERIVED CLOCK

FIGURE 3 - RECEIVER INPUT TIMING FOR ARINC 429

TESTA

TESTB

DERIVED DATA

DERIVED CLOCK

ARINC Data Bits

28 29 30 31 32

Word Gap

4 Bit Periods Min.

FIGURE 4 - TEST INPUT TIMING FOR ARINC 429

DERIVED DATA

DATA RDY

READ

D0 - D15

32nd

ARINC bit

tDRDY

tRDYCLR

tRDPW

1st 16-bits

tRR

2nd 16-bits

tRD

tFD

VALID

VALID

FIGURE 5 - RECEIVER PARALLEL DATABUS TIMING

1

2

+10V

0V

-10V

1

2

+5V

0V

+5V

0V

HOLT INTEGRATED CIRCUITS

5

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