IDT7026S35J 데이터 시트보기 (PDF) - Integrated Device Technology
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IDT7026S35J Datasheet PDF : 18 Pages
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IDT7026S/L
High-Speed 16K x 16 Dual-Port Static RAM
Truth Table IV —
Address BUSY Arbitration
Inputs
Outputs
CEL CER
AOL-A13L
AOR-A13R
BUSYL(1) BUSYR(1)
Function
X
X
NO MATCH
H
H
Normal
HX
MATCH
H
H
Normal
XH
MATCH
H
H
Normal
L
L
MATCH
(2)
(2)
Write Inhibit(3)
NOTES:
2939 tbl 16
1. Pins BUSYL and BUSYR are both outputs when the part is configured as a
master. Both are inputs when configured as a slave. BUSYX outputs on the
IDT7026 are push pull, not open drain outputs. On slaves the BUSYX input
internally inhibits writes.
2. LOW if the inputs to the opposite port were stable prior to the address and enable
inputs of this port. HIGH if the inputs to the opposite port became stable after the
address and enable inputs of this port. If tAPS is not met, either BUSYL or BUSYR
= LOW will result. BUSYL and BUSYR outputs cannot be LOW simultaneously.
3. Writes to the left port are internally ignored when BUSYL outputs are driving LOW
regardless of actual logic level on the pin. Writes to the right port are internally
ignored when BUSYR outputs are driving LOW regardless of actual logic level
on the pin.
Military, Industrial and Commercial Temperature Ranges
Width Expansion with BUSY Logic
Master/Slave Arrays
When expanding an IDT7026 RAM array in width while using BUSY
logic, one master part is used to decide which side of the RAM array will
receive a BUSY indication, and to output that indication. Any number of
slaves to be addressed in the same address range as the master use the
BUSY signal as a write inhibit signal. Thus on the IDT7026 RAM the BUSY
pin is an output if the part is used as a master (M/S pin = VIH), and the BUSY
pin is an input if the part used as a slave (M/S pin = VIL) as shown in
Figure 3.
If two or more master parts were used when expanding in width, a split
decision could result with one master indicating BUSY on one side of the
MASTER
Dual Port
RAM
BUSYL
CE
BUSYR
SLAVE
Dual Port
RAM
BUSYL
CE
BUSYR
BUSYL
MASTER
Dual Port
RAM
BUSYL
CE
BUSYR
SLAVE
Dual Port
RAM
BUSYL
CE
BUSYR
BUSYR
Functional Description
The IDT7026 provides two ports with separate control, address and
I/O pins that permit independent access for reads or writes to any location
in memory. The IDT7026 has an automatic power down feature controlled
by CE. The CE controls on-chip power down circuitry that permits the
respective port to go into a standby mode when not selected (CE = VIH).
When a port is enabled, access to the entire memory array is permitted.
Busy Logic
Busy Logic provides a hardware indication that both ports of the RAM
have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is “Busy”.
The BUSY pin can then be used to stall the access until the operation on
the other side is completed. If a write operation has been attempted from
the side that receives a BUSY indication, the write signal is gated internally
to prevent the write from proceeding.
The use of BUSY logic is not required or desirable for all applications.
In some cases it may be useful to logically OR the BUSY outputs together
and use any BUSY indication as an interrupt source to flag the event of
an illegal or illogical operation. If the write inhibit function of BUSY logic is
not desirable, the BUSY logic can be disabled by placing the part in slave
mode with the M/S pin. Once in slave mode the BUSY pin operates solely
as a write inhibit input pin. Normal operation can be programmed by tying
the BUSY pins HIGH. If desired, unintended write operations can be
prevented to a port by tying the BUSY pin for that port LOW.
The BUSY outputs on the IDT 7026 RAM in master mode, are push-
pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the BUSY indication for the
resulting array requires the use of an external AND gate.
2939 drw 16
Figure 3. Busy and chip enable routing for both width and depth
expansion with IDT7026 RAMs.
array and another master indicating BUSY on one other side of the array.
This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.
The BUSY arbitration on a master is based on the chip enable and
address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a BUSY flag to be output from the master before the actual write
pulse can be initiated with either the R/W signal or the byte enables. Failure
to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.
Semaphores
The IDT7026 is an extremely fast Dual-Port 16K x 16 CMOS Static
RAM with an additional 8 address locations dedicated to binary semaphore
flags. These flags allow either processor on the left or right side of the Dual-
Port RAM to claim a privilege over the other processor for functions defined
by the system designer’s software. As an example, the semaphore can
be used by one processor to inhibit the other from accessing a portion of
the Dual-Port RAM or any other shared resource.
The Dual-Port RAM features a fast access time, and both ports are
completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
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