ST7263BKX 데이터 시트보기 (PDF) - STMicroelectronics
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ST7263BKX Datasheet PDF : 186 Pages
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ST7263Bxx
16 Known limitations
Known limitations
16.1
Note:
PA2 limitation with OCMP1 enabled
Description
This limitation affects only Rev B Flash devices (with Internal Sales Type 72F63Bxxxxx$x7);
it has been corrected in Rev W Flash devices (with Internal Sales Type 72F63Bxxxxx$x9).
Refer to Figure 85 on page 183
When output Compare 1 function (OCMP1) on pin PA6 is enabled by setting the OC1E bit in
the TCR2 register, pin PA2 is also affected.
In particular, PA2 is switched to its alternate function mode, SCL. As a consequence, the
PA2 pin is forced to be floating (steady level of I2C clock) even if port configuration
(PADDR+PADR) has set it as output low. However, it can be still used as an input or can be
controlled by the I2C cell when enabled (where I2C is available).
16.2
Unexpected RESET fetch
Description
If an interrupt request occurs while a "POP CC" instruction is executed, the interrupt
controller does not recognise the source of the interrupt and, by default, passes the RESET
vector address to the CPU.
Workaround
To solve this issue, a "POP CC" instruction must always be preceded by a "SIM" instruction.
16.3
16.4
USB behavior with LVD disabled
Description
If the LVD is disabled on 4K and 8K ROM devices (ST7263BK1M1, ST72BK2M1,
ST7263BKB1, ST7263BK2B1 only), the USB is disabled by hardware. The LVD is
consequently forced by ST to ‘0’ (LVD enabled). Refer to the ST7263Bx option list for details.
I2C multimaster
Description
In multimaster configurations, if the ST7 I2C receives a START condition from another I2C
master after the START bit is set in the I2CCR register and before the START condition is
generated by the ST7 I2C, it may ignore the START condition from the other I2C master. In
this case, the ST7 master will receive a NACK from the other device. On reception of the
NACK, ST7 can send a re-start and Slave address to re-initiate communication
Doc ID 7516 Rev 8
181/186
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