28LV256 데이터 시트보기 (PDF) - Turbo IC Inc
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28LV256 Datasheet PDF : 4 Pages
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Turbo IC, Inc.
28LV256
LOW VOLTAGE CMOS
256K ELECTRICALLY ERASABLE PROGRAMMABLE ROM
32K X 8 BIT EEPROM
FEATURES:
• 200 ns Access Time
• Automatic Page Write Operation
Internal Control Timer
Internal Data and Address Latches for 64 Bytes
• Fast Write Cycle Times
Byte or Page Write Cycles: 10 ms
Time to Rewrite Complete Memory: 5 sec
Typical Byte Write Cycle Time: 160 µsec
• Software Data Protection
• Low Power Dissipation
20 mA Active Current
35 µA CMOS Standby Current
• Direct Microprocessor End of Write Detection
Data Polling
• High Reliability CMOS Technology with Self Redundant
EEPROM Cell
Typical Endurance: 100,000 Cycles
Data Retention: 10 Years
• TTL and CMOS Compatible Inputs and Outputs
• Single 3.3 V ± 10% Power Supply for Read and
Programming Operations
• JEDEC Approved Byte-Write Pinout
DESCRIPTION:
The Turbo IC 28LV256 is a 32K X 8 EEPROM fabricated
with Turbo’s proprietary, high reliability, high performance
CMOS technology. The 256K bits of memory are organized
as 32K by 8 bits. The device offers access time of 200 ns
with power dissipation below 66 mW.
The 28LV256 has a 64-bytes page write operation, enabling
the entire memory to be typically written in less than 5.0
seconds. During a write cycle, the address and 1 to 64 bytes
of data are internally latched, freeing the address and data
bus for other microprocessor operations. The programming
process is automatically controlled by the device using an
internal control timer. Data polling on one or all I/O can be
used to detect the end of a programming cycle. In addition,
the 28LV256 includes an user-optional software data write
mode offering additional protection against unwanted (false)
write. The device utilizes an error protected self redundant
cell for extended data retention and endurance.
A7 A14 VCC A13
A12 NC WE
A6 5 4 3 2 1 32 31 3029 A8
A5 6
28 A9
A4 7
27 A11
A3 8
26 NC
A2 9
25 OE
A1 10
24 A10
A0 11
23 CE
NC 12
22 I/O7
I/O0
13
21
14 15 16 17 18 19 20
I/O6
I/O1 GND I/O3 I/O5
I/O2 NC I/O4
32 pins PLCC
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O0 11
I/O1 12
I/O2 13
GND 14
28 VCC
27 WE
26 A13
25 A8
24 A9
23 A11
22 OE
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
28 pins PDIP
A14 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
I/O0 11
I/O1 12
I/O2 13
GND 14
OE 1
28 VCC A11
2
A9 3
27 WE
A8
4
A13 5
26 A13 WE
6
VCC 7
25 A8
A14
8
A12 9
24 A9
A7
10
A6 11
23 A11
A5
12
A4 13
22 OE
A3
14
21 A10
20 CE
19 I/O7
18 I/O6
17 I/O5
16 I/O4
15 I/O3
28 pins SOIC (SOG)
28 pins TSOP
28 A10
27
CE
26 I/O7
25
I/O6
24 I/O5
23
I/O4
22 I/O3
21
GND
20 I/O2
19
I/O1
18 I/O0
17
A0
16 A1
15
A2
PIN DESCRIPTION
ADDRESSES (A0 - A14)
The Addresses are used to select an 8 bits
memory location during a write or read opera-
tion.
OUTPUT ENABLE (OE)
The Output Enable input activates the output buff-
ers during the read operations.
CHIP ENABLES (CE)
The Chip Enable input must be low to enable all
read/write operation on the device. By setting CE
high, the device is disabled and the power con-
sumption is extremely low with the standby cur-
rent below 35 µA.
WRITE ENABLE (WE)
The Write Enable input initiates the writing of data
into the memory.
DATA INPUT/OUTPUT (I/O0-I/O7)
Data Input/Output pins are used to read data out
of the memory or to write Data into the memory.
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