Unit Loading/Fan Out
Pin Names
Description
D0–D7
CE
CP
Q0–Q7
Data Inputs
Clock Enable (Active LOW)
Clock Pulse Input
Data Outputs
Mode Select-Function Table
U.L.
HIGH/LOW
1.0/1.0
1.0/1.0
1.0/1.0
50/33.3
Input IIH/IIL
Output IOH/IOL
20 µA/−0.6 mA
20 µA/−0.6 mA
20 µA/−0.6 mA
−1 mA/20 mA
Inputs
Operating Mode
Load “1”
Load “0”
Hold
CP
CE
I
I
h
(Do Nothing)
X
H
H = HIGH Voltage Level
h = HIGH Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
L = LOW Voltage Level
I = LOW Voltage Level one setup time prior to the LOW-to-HIGH Clock Transition
X = Immaterial
= LOW-to-HIGH Clock Transition
Logic Diagram
Output
Dn
Qn
h
H
I
L
X
No Change
X
No Change
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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