CY7C1061AV33-10ZXC 데이터 시트보기 (PDF) - Cypress Semiconductor

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CY7C1061AV33-10ZXC

16-Mbit (1 M × 16) Static RAM

Cypress Semiconductor 

CY7C1061AV33

Capacitance

Parameter [6]

Description

CIN

COUT

Input capacitance

I/O capacitance

Test Conditions

TA = 25 C, f = 1 MHz, VCC = 3.3 V

TSOP II

6

8

FBGA

Unit

8

pF

10

pF

AC Test Loads and Waveforms

Figure 3. AC Test Loads and Waveforms [7]

OUTPUT

50 

VTH = 1.5 V

3.3 V

R1 317 

Z0 = 50 

(a)

30 pF* * Capacitive Load consists of all

components of the test environment.

OUTPUT

5 pF*

3.3 V

ALL INPUT PULSES

90%

90%

INCLUDING

JIG AND

SCOPE (b)

GND

10%

10%

Rise time > 1 V/ns

(c)

Fall time:

> 1 V/ns

R2

351

Data Retention Waveform

Figure 4. Data Retention Waveform

DATA RETENTION MODE

VCC

3.0 V

VDR > 2 V

3.0 V

tCDR

tR

CE

Notes

6. Tested initially and after any design or process changes that may affect these parameters.

7.

Valid SRAM operation does not occur until the power supplies have reached the minimum

operating VDD, normal SRAM operation can begin including reduction in VDD to the data

roepteernatitoinng(VVDCDCD(3R.,02V.0).VA)svsooltoangea.s

1

ms

(Tpower)

after

reaching

the

minimum

Document Number: 38-05256 Rev. *L

Page 6 of 17

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