WM8721L(2004) 데이터 시트보기 (PDF) - Wolfson Microelectronics plc
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WM8721L Datasheet PDF : 37 Pages
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WM8721 / WM8721L
Production Data
Recommended values are C1 = 220uF (10V electrolytic), R1 = 47k
C1 forms a DC blocking capacitor to isolate the dc of the HPOUT from the headphones. R1 form a
pull down resistor to discharge C1 to prevent the voltage at the connection to the headphones from
rising to a level that may damage the headphones.
DEVICE OPERATION
DEVICE RESETTING
The WM8721 contains a power on reset circuit that resets the internal state of the device to a known
condition. The power on reset is applied as DCVDD powers on and released only after the voltage
level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on
threshold voltage then the power on reset is re-applied. The threshold voltages and associated
hysteresis are shown in the Electrical Characteristics table.
The user also has the ability to reset the device to a known state under software control as shown in
the table below.
REGISTER
ADDRESS
0001111
Reset Register
BIT
LABEL
8:0 RESET
Table 5 Software Control of Reset
DEFAULT
DESCRIPTION
not reset
Reset Register
Writing 000000000 to register resets
device
When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and
released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the
ACK signal (approximately 1 SCLK period, refer to Figure 19).
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. The external master system clock can be applied directly through the MCLK input pin
with no software configuration necessary.
Note that on the WM8721, MCLK is used to derive clocks for the DAC path. The DAC path consists
of DAC sampling clock, DAC digital filter clock and DAC digital audio interface timing. In a system
where there are a number of possible sources for the reference clock it is recommended that the
clock source with the lowest jitter be used to optimise the performance of the DAC.
CORE CLOCK
The WM8721 DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by
software as shown in Table 6 below.
REGISTER
ADDRESS
0001000
Sampling
Control
BIT
LABEL
6
CLKIDIV2
Table 6 Software Control of Core Clock
DEFAULT
0
DESCRIPTION
Core Clock divider select
1 = Core Clock is MCLK divide by 2
0 = Core Clock is MCLK
Having a programmable MCLK divider allows the device to be used in applications where higher
frequency master Clocks are available. For example the device can support 512fs master clocks
whilst fundamentally operating in a 256fs mode.
DIGITAL AUDIO INTERFACES
WM8721 may be operated in either one of the 4 offered audio interface modes. These are:
• Right justified
• Left justified
•
I2S
• DSP mode
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PD Rev 4.0 November 2004
16
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