NCP1654BD200R2G 데이터 시트보기 (PDF) - ON Semiconductor
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NCP1654BD200R2G
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NCP1654BD200R2G Datasheet PDF : 23 Pages
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NCP1654
PRINCIPLE OF NCP1654 SCHEME
CCM PFC Boost
A CCM PFC boost converter is shown in Figure 31. The
input voltage is a rectified 50 ro 60 Hz sinusoidal signal.
The MOSFET is switching at a high frequency (typically
65/133/200 kHz in NCP1654) so that the inductor current
IL basically consists of high and low−frequency
components.
Filter capacitor Cfilter is an essential and very small value
capacitor in order to eliminate the high−frequency
component of the inductor IL. This filter capacitor cannot
be too bulky because it can pollute the power factor by
distorting the rectified sinusoidal input voltage.
Iin
Vin
L
IL
Cfilter
RSENSE
Vout
+
Output
Voltage
Cbulk
Figure 31. CCM PFC Boost Converter
PFC Methodology
The NCP1654 uses a proprietary PFC methodology
particularly designed for CCM operation. The PFC
methodology is described in this section.
IL
Iin
The input filter capacitor Cfilter and the front−ended EMI
filter absorbs the high−frequency component of inductor
current IL. It makes the input current Iin a low−frequency
signal only of the inductor current.
Iin + IL*50
(eq. 2)
where
Iin is the input AC current.
IL is the inductor current.
IL−50 supposes a 50 Hz operation. The suffix 50 means
it is with a 50 Hz bandwidth of the original IL.
From (Equation 1) and (Equation 2), the input
impedance Zin is formulated.
Zin
+
Vin
Iin
+
T
*
T
t1
Vout
IL*50
(eq. 3)
where Zin is input impedance.
Power factor is corrected when the input impedance Zin
in (Equation 3) is constant or varies slowly in the 50 or 60
Hz bandwidth.
Ich
01
Cramp
VM Vref
PFC Modulation
-
+
+
RQ
Vramp
S
Clock
Vref
t1
t2
T
Time
Figure 32. Inductor Current in CCM
As shown in Figure 32, the inductor current IL in a
switching period T includes a charging phase for duration
t1 and a discharging phase for duration t2. The voltage
conversion ratio is obtained in (Equation 1).
Vout
Vin
+
t1
)
t2
t2
+
T
T
*
t1
Vin
+
T
*
T
t1
Vout
(eq. 1)
where
Vout is the output voltage of PFC stage,
Vin is the rectified input voltage,
T is the switching period,
t1 is the MOSFET on time, and
t2 is the MOSFET off time.
Vramp
VM
VM without
Filtering
Clock
Latch Set
Latch Reset
Output
Inductor
Current
Figure 33. PFC Duty Modulation and Timing Diagram
The PFC modulation and timing diagram is shown in
Figure 33. The MOSFET on time t1 is generated by the
intersection of reference voltage VREF and ramp voltage
Vramp. A relationship in (Equation 4) is obtained.
Vramp
+
Vm
)
Icht1
Cramp
+
VREF
(eq. 4)
where
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