W78E058B 데이터 시트보기 (PDF) - Winbond

부품명

상세내역

제조사

W78E058B

8-BIT MICROCONTROLLER

Winbond 

W78E58B/W78E058B

7.3.3 Data Read Cycle

PARAMETER

ALE Low to RD Low

RD Low to Data Valid

Data Hold from RD High

Data Float from RD High

RD Pulse Width

SYMBOL

TDAR

TDDA

TDDH

TDDZ

TDRD

MIN.

3 TCP-∆

-

0

0

6 TCP-∆

Notes:

1. Data memory access time is 8 TCP.

2. "∆" (due to buffer driving delay and wire loading) is 20 nS.

TYP.

-

-

-

-

6 TCP

MAX.

3 TCP+∆

4 TCP

2 TCP

2 TCP

-

UNIT

nS

nS

nS

nS

nS

NOTES

1, 2

1

2

7.3.4 Data Write Cycle

PARAMETER

ALE Low to WR Low

Data Valid to WR Low

Data Hold from WR High

WR Pulse Width

SYMBOL

TDAW

TDAD

TDWD

TDWR

Note: "∆" (due to buffer driving delay and wire loading) is 20 nS.

MIN.

3 TCP-∆

1 TCP-∆

1 TCP-∆

6 TCP-∆

TYP.

-

-

-

6 TCP

MAX.

3 TCP+∆

-

-

-

UNIT

nS

nS

nS

nS

7.3.5 Port Access Cycle

PARAMETER

Port Input Setup to ALE Low

Port Input Hold from ALE Low

Port Output to ALE

SYMBOL

TPDS

TPDH

TPDA

MIN.

1 TCP

0

1 TCP

TYP.

-

-

-

MAX.

-

-

-

UNIT

nS

nS

nS

Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to

ALE, since it provides a convenient reference.

- 24 -

Share Link: