LTC2141I 데이터 시트보기 (PDF) - Linear Technology
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LTC2141I Datasheet PDF : 36 Pages
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LTC2142-12/
LTC2141-12/LTC2140-12
TIMING DIAGRAMS
Full Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
CH 1
ANALOG
INPUT
CH 2
ANALOG
INPUT
ENC–
ENC+
D1_0 - D1_11, OF1
tAP
A
tAP
B
A+1
tH
B+1
tL
A+2
B+2
A+3
B+3
A+4
B+4
tD
A–6
A–5
A–4
A–3
A–2
D2_0 - D2_11, OF2
CLKOUT+
CLKOUT –
B–6
tC
B–5
B–4
B–3
B–2
21421012 TD01
CH 1
ANALOG
INPUT
CH 2
ANALOG
INPUT
ENC–
ENC+
D1_0_1
•••
D1_10_11
D2_0_1
•••
D2_10_11
Double Data Rate CMOS Output Mode Timing
All Outputs Are Single-Ended and Have CMOS Levels
tAP
A
tAP
B
A+1
tH
B+1
tL
A+2
B+2
A+3
B+3
A+4
B+4
tD
BIT 0
A-6
BIT 1 BIT 0
A-6
A-5
tD
BIT 1
A-5
BIT 0
A-4
BIT 1
A-4
BIT 0
A-3
BIT 1
A-3
BIT 0
A-2
BIT 10 BIT 11 BIT 10 BIT 11 BIT 10 BIT 11 BIT 10 BIT 11 BIT 10
A-6
A-6
A-5
A-5
A-4
A-4
A-3
A-3
A-2
BIT 0
B-6
BIT 1 BIT 0
B-6
B-5
BIT 1
B-5
BIT 0
B-4
BIT 1
B-4
BIT 0
B-3
BIT 1
B-3
BIT 0
B-2
BIT 10 BIT 11 BIT 10 BIT 11 BIT 10 BIT 11 BIT 10 BIT 11 BIT 10
B-6
B-6
B-5
B-5
B-4
B-4
B-3
B-3
B-2
OF2_1
CLKOUT+
CLKOUT –
OF
OF
OF
OF
OF
OF
OF
OF
OF
B-6
A-6
B-5
A-5
B-4
A-4
B-3
A-3
B-2
tC
tC
21421012 TD02
21421012p
9
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