
Truth Table
Shutdown Reset
H
H
H
H→L
L
H
L
L
L→H
L
Output
Normal Operation
Normal Operation, No Change
Off, Not Latched
Off, Latched
Off, Latched, No Change
Shutdown Timing Waveforms
1.5V
Sense
0
VDD
Output
0
50%
tR ≤ 10ns
td
90%
HV9110/HV9112/HV9113
VDD
Shutdown
0
VDD
Output
0
50%
tF ≤ 10ns
tSD
90%
VDD
Shutdown
0
VDD
Reset
0
50%
t SW
t LW
50%
50%
50%
50%
t RW
tR, tF ≤ 10ns
Functional Block Diagram
10 (14)
VREF
1 (20)
BIAS
6 (9)
VDD
2 (3)
+VIN
FB
14
(19)
COMP
13
(18)
Error
Amplifier
–
Discharge
9
(12)
OSC
In
OSC
Out
8 (11) 7 (10)
OSC
+
4V
REF
GEN
2V –
+
+
–
Current
Sources
To
Internal 1.2V
Circuits
Modulator
Comparator
Current Limit
Comparator
R
Q
S
8.1V
Undervoltage
– Comparator
+
8.6V
Pre-regulator/Startup
T
Q
9113 9110
9112
V DD
S
Q
R
To V DD
4 (6)
Output
5 (8)
-V IN
3 (5)
Current Sense
11 (16)
Shutdown
Reset
12 (17)
Pin numbers in parentheses are for PLCC package
4