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SI4785

Si47XX ANTENNA, SCHEMATIC, LAYOUT, AND DESIGN GUIDELINES

Silicon Laboratories 

AN383

 Do not route VCO pin 1 and 20 (NC). These pins must be left floating to guarantee proper operation.

 Place the Si47xx close to the antenna(s) to minimize antenna trace length and capacitance and to minimize

inductive and capacitive coupling. This recommendation must be followed for optimal device performance.

 Route the antenna trace over an unobstructed ground plane to minimize antenna loop area and inductive

coupling.

 Design, place, and route other circuits such that radiation in the band of interest is minimized.

 Tie unused pin(s) to GND, but do not tie No Connect (NC) pins to GND. For example, in Si471x FM transmitter

analog audio input mode, DFS pin 14 and DIN pin 13 are not used; therefore, these two pins should be tied to

GND.

2.6.1. Emissions Mitigation Checklist

The following design checklist summarizes the guidelines for mitigating emissions in the 3–4 GHz range, if

applicable.

 Place F1 as close as possible to FMI pin 2.

 Place C14 as close as possible to FMI pin 2.

 Place C5 even though it is designated as NP, it should be as close as possible to FMI pin2.

 On the Si4704/05/06/1x/2x products:

Place C4 as close as possible to LPI/TXO pin 4 and RFGND pin 3.

Place L1 as close as possible to LPI/TXO pin 4.

 On Si473x products:

Place C16 as close as possible to AMI pin 4 and RFGND pin 3.

Place L2 as close as possible to AMI pin 4.

Place C17 as close as possible to AMI pin 4 and RFGND pin 3.

 Place C15 and C18 as close as possible to GPO1 & GPO2 pins.

 Place R19 and R20 as close as possible to GPO1 & GPO2 pins.

 Route FMI pin 2 to GND/RFGND if the pin functionality is not used.

 Route TXO/AMI/LPI pin 4 to GND/RFGND if the pin functionality is not used.

 Flood the primary and secondary layers with ground and place stitching vias between the GND fill and GND

plane.

 Shunt capacitors C4, C5, C14, C15, C16, C17, and C18 should be connected directly to the GND plane on top

layer.

 Do not use heat relief for these pad's GND connection.

 Connecting shunt capacitors only to a via to the GND plane is not sufficient; though it is permissible to have

such a via if the top GND plane is also connected.

 If additional space is available, increase the size of RFGND trace by moving FMI and AMI signal paths further

apart.

 Avoid unnecessary breaks in the top ground fill between the Si47xx and the system GND connection. The goal

is to have the path from shunt capacitors as direct, unbroken, and wide as possible.

 Rotate the Si47xx (as necessary) in order to create the best ground path for the FMI and GPO mitigation as

these are the greater contributors to emissions.

 Orient the shunt capacitor(s) on FMI (C14) to the right of the trace (towards pin 1).

 Orient the shunt capacitors on AMI (C16 & C17) to the right of the trace (toward RFGND, pin 3).

Rev. 0.8

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