STK14C88-W45 데이터 시트보기 (PDF) - Unspecified
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STK14C88-W45 Datasheet PDF : 12 Pages
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SRAM READ CYCLES #1 & #2
SYMBOLS
NO.
#1, #2
Alt.
PARAMETER
1
tELQV
2
tAVAVg
3
tAVQVh
4
tGLQV
5
tAXQXh
6
tELQX
7
tEHQZ
8
tGLQX
9
tGHQZi
10
tELICCH
11
tEHICCL
tACS
tRC
tAA
tOE
tOH
tLZ
tHZ
tOLZ
tOHZ
tPA
tPS
Chip Enable Access Time
Read Cycle Time
Address Access Time
Output Enable to Data Valid
Output Hold after Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Note g: W and HSB must be high during SRAM READ cycles.
Note h: Device is continuously selected with E and G both low.
Note i: Measured ± 200mV from steady state output voltage.
SRAM READ CYCLE #1: Address Controlledg, h
ADDRESS
DQ (DATA OUT)
5
tAXQX
2
tAVAV
3
tAVQV
SRAM READ CYCLE #2: E Controlledg
ADDRESS
2
tAVAV
1
tELQV
E
6
tELQX
G
DQ (DATA OUT)
ICC
8
tGLQX
4
tGLQV
10
tELICCH
STANDBY
ACTIVE
STK14C88-M
(VCC = 5.0V ± 10%)e
STK14C88-35M
MIN
MAX
STK14C88-45M
MIN
MAX
UNITS
35
45
ns
35
45
ns
35
45
ns
15
20
ns
3
3
ns
5
5
ns
13
15
ns
0
0
ns
13
15
ns
0
0
ns
35
45
ns
DATA VALID
11
tEHICCL
7
tEHQZ
9
tGHQZ
DATA VALID
April 1999
5-45
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