M38031G1H-XXXSP 데이터 시트보기 (PDF) - Renesas Electronics
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M38031G1H-XXXSP Datasheet PDF : 92 Pages
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3803 Group (Spec.H QzROM version)
PRELIMINARY
Notice: This is not a final specification.
Some parametric limits are subject to change.
PIN DESCRIPTION
Table 4 Pin description
Pin
VCC, VSS
CNVSS
Name
Power source
CNVSS input
VREF
AVSS
RESET
XIN
Reference
voltage
Analog power
source
Reset input
Clock input
XOUT
Clock output
P00/AN8−
P07/AN15
P10/INT41
P11/INT01
P12−P17
I/O port P0
I/O port P1
P20-P27
I/O port P2
P30/DA1
P31/DA2
P32, P33
P34/RXD3
P35/TXD3
P36/SCLK3
P37/SRDY3
P40/INT40/XCOUT
P41/INT00/XCIN
I/O port P3
I/O port P4
P42/INT1
P43/INT2
P44/RXD1
P45/TXD1
P46/SCLK1
P47/SRDY1/CNTR2
P50/SIN2
P51/SOUT2
P52/SCLK2
P53/SRDY2
I/O port P5
P54/CNTR0
P55/CNTR1
P56/PWM
P57/INT3
P60/AN0−
P67/AN7
I/O port P6
Functions
Function except a port function
• Apply voltage of 1.8 V − 5.5 V to VCC, and 0 V to VSS.
• This pin controls the operation mode of the chip and is shared with the VPP pin which is the
power source input pin for programming the built-in QzROM.
• Normally connected to VSS.
• Reference voltage input pin for A/D and D/A converters.
• Analog power source input pin for A/D and D/A converters.
• Connect to VSS.
• Reset input pin for active “L”.
• Input and output pins for the clock generating circuit.
• Connect a ceramic resonator or quartz-crystal oscillator between the XIN and XOUT pins to set
the oscillation frequency.
• When an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin
open.
• 8-bit CMOS I/O port.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit.
• P20 − P27 (8 bits) are enabled to output large current for
LED drive.
• A/D converter input pin
• Interrupt input pin
• 8-bit CMOS I/O port.
• D/A converter input pin
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level.
• P30, P31, P34 − P37 are CMOS 3-state output structure.
• Serial I/O3 function pin
• P32, P33 are N-channel open-drain output structure.
• Pull-up control of P30, P31, P34 − P37 is enabled in a bit unit.
• 8-bit CMOS I/O port.
• I/O direction register allows each pin to be individually
programmed as either input or output.
• CMOS compatible input level.
• CMOS 3-state output structure.
• Pull-up control is enabled in a bit unit.
• Interrupt input pin
• Sub-clock generating I/O pin
(resonator connected)
• Interrupt input pin
• Serial I/O1 function pin
• Serial I/O1, timer Z function pin
• Serial I/O2 function pin
• Timer X function pin
• Timer Y function pin
• PWM output pin
• Interrupt input pin
• A/D converter input pin
Rev.1.10 Nov 14, 2005 Page 6 of 91
REJ03B0166-0110
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