
■ Timing Diagram
MCLK
LRCK
BICK
[AK4145]
1/fCLK
tCLKH
tCLKL
VIH
VIL
dCLK=tCLKH x fCLK, tCLKL x fCLK
1/fs
tBCK
tBCKH
tBCKL
Figure 1. Clock Timing
VIH
VIL
VIH
VIL
VIH
LRCK
VIL
tBLR
tLRB
BICK
VIH
VIL
tSDS
tSDH
VIH
SDTI
VIL
Figure 2. Serial Interface Timing
Rev. 0.3-PB
-7-
2007/12