MT46V16M16TG-75Z 데이터 시트보기 (PDF) - Micron Technology
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MT46V16M16TG-75Z Datasheet PDF : 80 Pages
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256Mb: x4, x8, x16
DDR SDRAM
CK#
CK
CKE
COMMAND5
x4: A0-A9, A11
x8: A0-A9
x16: A0-A8
x4: A12
x8: A11, A12
x16: A9, A11, A12
A10
BA0, BA1
Figure 48: Bank Read - Without Auto Precharge
T0
T1
T2
T3
T4
T5 T5n T6 T6n T7
tIS tIH
tCK
tCH tCL
tIS tIH
NOP6
ACT
tIS tIH
RA
NOP6
READ2
Col n
NOP6
PRE7
NOP6
NOP6
RA
RA
tIS tIH
Bank x
tRCD
tRAS7
tRC
tIS tIH
3
Bank x
CL = 2
ALL BANKS
ONE BANK
Bank x4
tRP
DM
T8
ACT
RA
RA
RA
Bank x
Case 1: tAC (MIN) and tDQSCK (MIN)
DQS
DQ1
Case 2: tAC (MAX) and tDQSCK (MAX)
DQS
tLZ (MIN)
tRPRE
tDQSCK (MIN)
tLZ (MIN)
DO
n
tAC (MIN)
tRPRE
tDQSCK(MAX)
tRPST
tRPST
DQ1
DO
n
tAC (MAX)
tHZ (MAX)
DON’T CARE
TRANSITIONING DATA
NOTE:
1. DOn = data-out from column n; subsequent elements are provided in the programmed order.
2. Burst length = 4 in the case shown.
3. Disable auto precharge.
4. “Don’t Care” if A10 is HIGH at T5.
5. PRE = PRECHARGE; ACT = ACTIVE; RA = Row Address; and BA = Bank Address.
6. NOP commands are shown for ease of illustration; other commands may be valid at these times.
7. The PRECHARGE command can only be applied at T5 if tRAS minimum is met.
8. Refer to Figure 40 on page 65, Figure 41 on page 66, and Figure 42 on page 67 for detailed DQS and DQ timing.
09005aef8076894f
256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN
73
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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