MT46V16M16TG-75EL 데이터 시트보기 (PDF) - Micron Technology

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MT46V16M16TG-75EL

256Mb: x4, x8, x16 DDR SDRAM

Micron Technology 

256Mb: x4, x8, x16

DDR SDRAM

VDD

VDDQ

VTT1

tVTD1

Figure 44: Initialize and Load Mode Registers

((

))

((

))

((

))

VREF

CK#

CK

CKE

COMMAND6

DM

A0-A9,

A11, A12

A10

BA0, BA1

DQS

DQ

((

))

T0

T1

((

((

))

))

((

((

))

tCH tCL

))

LVCMOS

LOW LEVEL ( (

))

((

))

((

))

((

))

((

))

tIS tIH

tIS tIH

NOP

tCK

((

))

((

))

((

PRE

))

((

))

((

))

((

))

((

((

))

))

((

((

))

))

((

ALL BANKS ( (

))

))

((

((

))

tIS tIH ) )

((

((

))

))

((

((

))

))

Ta0

((

))

((

))

Tb0

((

))

((

))

Tc0

((

))

((

))

((

((

((

))

))

))

((

((

((

))

))

))

((

((

LMR

))

LMR

))

((

((

))

))

((

PRE

))

((

))

((

((

((

))

))

))

((

((

((

))

))

))

tIS tIH

((

CODE

))

((

))

tIS tIH

((

CODE

))

((

))

tIS tIH

CODE

CODE

((

((

))

))

((

((

))

))

( ( ALL BANKS

((

))

))

((

((

) ) tIS tIH ) )

((

((

((

BA0 = H, ) ) BA0 = L, ) )

))

BA1 = L ( (

BA1 = L ( (

((

))

))

))

Td0

((

))

((

))

((

))

((

))

((

AR

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

))

((

High-Z

))

((

((

((

((

((

))

))

))

))

))

((

))

T = 200µs

High-Z

Power-up: VDD and CK stable

((

((

((

((

((

))

))

))

))

))

tRP

tMRD

tMRD

Load Extended

Mode Register

Load Mode

Register2

tRP

200 cycles of CK3

tRFC

Te0

Tf0

((

))

((

))

((

))

((

))

((

AR

))

ACT5

((

))

((

))

((

))

((

))

RA

((

))

((

))

RA

((

))

((

))

BA

((

))

((

))

((

))

tRFC5

DON’T CARE

NOTE:

1. VTT is not applied directly to the device; however, tVTD should be greater than or equal to zero to avoid device latch-up. VDDQ, VTT, and VREF

must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power-up, even if VDD/VDDQ are 0V, provided a

minimum of 42W of series resistance is used between the VTT supply and the input pin. Once initialized, VREF must always be powered within

the specified range.

2. Reset the DLL with A8 = H while programming the operating parameters.

3. tMRD is required before any command can be applied, and 200 cycles of CK are required before a READ command can be issued.

4. The two AUTO REFRESH commands at Td0 and Te0 may be applied prior to the LOAD MODE REGISTER (LMR) command at Ta0.

5. Although not required by the Micron device, JEDEC specifies issuing another LMR command (A8 = L) prior to activating any

bank. If another LMR command is issued, the same operating parameters must be used as previously issued.

6. PRE = PRECHARGE command; LMR = LOAD MODE REGISTER command; AR = AUTO REFRESH command; ACT = ACTIVE com-

mand; RA = Row Address; and BA = Bank Address.

SYMBOL

tCH

tCL

tCK (2.5)

tCK (2)

tIHF

tISF

-6/6T/6T

MIN MAX

0.45 0.55

0.45 0.55

6

13

7.5 13

.75

.75

-75E/75Z

MIN MAX

0.45 0.55

0.45 0.55

7.5 13

7.5 13

.90

.90

-75

MIN MAX

0.45 0.55

0.45 0.55

7.5

13

10

13

0.90

0.90

UNITS

tCK

tCK

ns

ns

ns

ns

SYMBOL

tIHS

tISS

tMRD

tRFC

tRP

tVTD

-6/6T/6T

MIN MAX

0.8

0.8

15

72

18

0

-75E/75Z

MIN MAX

1

1

15

75

15

0

-75

MIN MAX

1

1

15

75

20

0

UNITS

ns

ns

ns

ns

ns

ns

09005aef8076894f

256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN

69

Micron Technology, Inc., reserves the right to change products or specifications without notice.

©2003 Micron Technology, Inc.

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