MT46V16M16BG-75 데이터 시트보기 (PDF) - Micron Technology
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MT46V16M16BG-75 Datasheet PDF : 80 Pages
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256Mb: x4, x8, x16
DDR SDRAM
Figure 40: x4, x8 Data Output Timing – tDQSQ, tQH, and Data Valid Window
T1
CK#
CK
tHP5
T2
T2n
T3
T3n
T4
tHP5
tHP5
tHP5
tDQSQ3
tDQSQ3
tHP5
tDQSQ3
tHP5
tDQSQ3
DQS1
DQ (Last data valid)
DQ2
DQ2
DQ2
DQ2
DQ2
DQ2
DQ (First data no longer valid)
DQ (Last data valid)
DQ (First data no longer valid)
All DQ and DQS, collectively6
Earliest signal transition
Latest signal transition
tQH4
tQH4
tQH4
tQH4
T2
T2n
T3
T3n
T2
T2n
T3
T3n
T2
T2n
T3
T3n
Data
Valid
window
Data
Valid
window
Data
Valid
window
Data
Valid
window
NOTE:
1. DQ transitioning after DQS transition define tDQSQ window. DQS transitions at T2 and at T2n are “early DQS,” at T3,
“nominal DQS,” and at T3n, “late DQS.”
2. For a x4, only two DQ apply.
3. tDQSQ is derived at each DQS clock edge and is not cumulative over time and begins with DQS transition and ends with
the last valid DQ transition.
4. tQH is derived from tHP: tQH = tHP - tQHS.
5. tHP is the lesser of tCL or tCH clock transition collectively when a bank is active.
6. The data valid window is derived for each DQS transitions and is defined as tQH minus tDQSQ.
09005aef8076894f
256MBDDRx4x8x16_2.fm - Rev. F 6/03 EN
65
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2003 Micron Technology, Inc.
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