CYUSB3031-BZXC(2013) 데이터 시트보기 (PDF) - Cypress Semiconductor

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CYUSB3031-BZXC
(Rev.:2013)

EZ-USB® FX3S SuperSpeed USB Controller

Cypress Semiconductor 

CYUSB3035

CLK

A[0:7]/DQ[0:15]

ADV#

CE#

OE#

RDY

Figure 22. Synchronous ADMux Interface – Burst Read Timing

2-cycle latency from OE# to Data

tCLK

tCLKH tCLKL

tS

tH

Valid Address

tS tH

tS

tAVOE

tOLZ

tCO

tCH

D0

D1

D2

tKW

D3

tHZ

tKW

Note:

1) External P-Port processor and FX3S work operate on the same clock edge

2) External processor sees RDY assert 2 cycles after OE # asserts andand sees RDY deassert a cycle after the last burst data appears on the output

3) Valid output data appears 2 cycle after OE # asserted. The last burst data is held until OE # deasserts

4) Burst size of 4 is shown. Transfer size for the operation must be a multiple of burst size. Burst size is usually power of 2. RDY will not deassert in the middle of the burst.

5) External processor cannot deassert OE in the middle of a burst. If it does so, any bytes remaining in the burst packet could get lost.

6) Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)

CLK

A[0:7]/DQ[0:15]

ADV#

CE#

WE#

RDY

Figure 23. Sync ADMux Interface – Burst Write Timing

2-cycle latency between

WE# and data being latched

tCLKH tCLKL

tS

tH

Valid Address

tS tH

tCLK

tS

tAVWE

tDS tDH

D0

D1

D2

tDH

D3

tKW

2-cycle latency between this clk edge and RDY

deassertion seen by the host

tKW

Note:

1) External P-Port processor and FX3S operate on the same clock edge

2) External processor sees RDY assert 2 cycles after WE # asserts and deasserts 3 cycles after the edge sampling the last burst data.

3) Transfer size for the operation must be a multiple of burst size. Burst size is usually power of 2. RDY will not deassert in the middle of the burst. Burst size of 4 is shown

4) External processor cannot deassert WE in the middle of a burst. If it does so, any bytes remaining in the burst packet could get lost.

5)Two cycle latency is shown for 0-100 MHz operation. Latency can be reduced by 1 cycle for operations at less than 50 MHz (this 1 cycle latency is not supported by the bootloader)

Document Number: 001-84160 Rev. *B

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