CYUSB3031-BZXC(2013) 데이터 시트보기 (PDF) - Cypress Semiconductor

부품명

상세내역

제조사

CYUSB3031-BZXC
(Rev.:2013)

EZ-USB® FX3S SuperSpeed USB Controller

Cypress Semiconductor 

CYUSB3035

Table 6. Entry and Exit Methods for Low-Power Modes (continued)

Low-Power Mode

Characteristics

Methods of Entry

Methods of Exit

Suspend Mode ■ The power consumption in this mode

with USB 3.0 PHY does not exceed ISB2

Disabled (L2)

■ USB 3.0 PHY is disabled and the USB

interface is in suspend mode

■ The clocks are shut off. The PLLs are

disabled

■ All I/Os maintain their previous state

■ USB interface maintains the previous

state

■ Firmware executing on ARM926EJ-S ■ D+ transitioning to low

core can put FX3S into suspend mode. or high

For example, on USB suspend

condition, firmware may decide to put

FX3S into suspend mode

■ D- transitioning to low or

high

■ External Processor, through the use of

mailbox registers can put FX3S into

■ Impedance change on

OTG_ID pin

suspend mode

■ Resume condition on

SSRX±

■ Detection of VBUS

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off

individually

■ The states of the configuration registers,

buffer memory and all internal RAM are

maintained

■ Level detect on

UART_CTS (program-

mable polarity)

■ GPIF II interface

assertion of CTL[0]

■ Assertion of RESET#

■ All transactions must be completed

before FX3S enters Suspend mode

(state of outstanding transactions are not

preserved)

■ The firmware resumes operation from

where it was suspended (except when

woken up by RESET# assertion)

because the program counter does not

reset

Standby Mode

(L3)

■ The power consumption in this mode ■ Firmware executing on ARM926EJ-S

does not exceed ISB3

core or external processor configures

■ All configuration register settings and

the appropriate register

program/data RAM contents are

preserved. However, data in the buffers

or other parts of the data path, if any, is

not guaranteed. Therefore, the external

processor should take care that the data

needed is read before putting FX3S into

this Standby Mode

■ Detection of VBUS

■ Level detect on

UART_CTS (Program-

mable Polarity)

■ GPIF II interface

assertion of CTL[0]

■ Assertion of RESET#

■ The program counter is reset after waking

up from Standby

■ GPIO pins maintain their configuration

■ Crystal oscillator is turned off

■ Internal PLL is turned off

■ USB transceiver is turned off

■ ARM926EJ-S core is powered down.

Upon wakeup, the core re-starts and runs

the program stored in the program/data

RAM

■ Power supply for the wakeup source and

core power must be retained. All other

power domains can be turned on/off

individually

Document Number: 001-84160 Rev. *B

Page 13 of 50

Share Link: