Table 3-1. TFBGA361 Pin Description (Continued)
Primary
Alternate
PIO Peripheral A PIO Peripheral B PIO Peripheral C Reset State
Pin Power Rail I/O Type
Signal, Dir, PU,
Signal Dir Signal Dir Signal Dir Signal Dir Signal Dir PD, HiZ, ST
B12 VDDIODDR DDR_IO
DDR_D26 I/O
–
–
–
–
–
–
–
–
I, HiZ
C12 VDDIODDR DDR_IO
DDR_D27 I/O
–
–
–
–
–
–
–
–
I, HiZ
F11 VDDIODDR DDR_IO
DDR_D28 I/O
–
–
–
–
–
–
–
–
I, HiZ
C11 VDDIODDR DDR_IO
DDR_D29 I/O
–
–
–
–
–
–
–
–
I, HiZ
D11 VDDIODDR DDR_IO
DDR_D30 I/O
–
–
–
–
–
–
–
–
I, HiZ
B11 VDDIODDR DDR_IO
DDR_D31 I/O
–
–
–
–
–
–
–
–
I, HiZ
L16 VDDIODDR DDR_IO DDR_DQM0 O
–
–
–
–
–
–
–
– O, LOW
J16 VDDIODDR DDR_IO DDR_DQM1 O
–
–
–
–
–
–
–
– O, LOW
D13 VDDIODDR DDR_IO DDR_DQM2 O
–
–
–
–
–
–
–
– O, LOW
F12 VDDIODDR DDR_IO DDR_DQM3 O
–
–
–
–
–
–
–
– O, LOW
J19 VDDIODDR DDR_IO DDR_DQS0 I/O
–
–
–
–
–
–
–
– O, LOW
F19 VDDIODDR DDR_IO DDR_DQS1 I/O
–
–
–
–
–
–
–
– O, LOW
A15 VDDIODDR DDR_IO DDR_DQS2 I/O
–
–
–
–
–
–
–
– O, LOW
A12 VDDIODDR DDR_IO DDR_DQS3 I/O
–
–
–
–
–
–
–
– O, LOW
K19 VDDIODDR DDR_IO DDR_DQSN0 I/O
–
–
–
–
–
–
–
– O, HIGH
G19 VDDIODDR DDR_IO DDR_DQSN1 I/O
–
–
–
–
–
–
–
– O, HIGH
A16 VDDIODDR DDR_IO DDR_DQSN2 I/O
–
–
–
–
–
–
–
– O, HIGH
A13 VDDIODDR DDR_IO DDR_DQSN3 I/O
–
–
–
–
–
–
–
– O, HIGH
B16 VDDIODDR DDR_IO
DDR_CS O
–
–
–
–
–
–
–
– O, LOW
A18 VDDIODDR DDR_IO
DDR_CLK O
–
–
–
–
–
–
–
–
O
A19 VDDIODDR DDR_IO DDR_CLKN O
–
–
–
–
–
–
–
–
O
D15 VDDIODDR DDR_IO
DDR_CKE O
–
–
–
–
–
–
–
– O, LOW
B17 VDDIODDR DDR_IO
DDR_RAS O
–
–
–
–
–
–
–
– O, LOW
A17 VDDIODDR DDR_IO
DDR_CAS O
–
–
–
–
–
–
–
– O, LOW
E16 VDDIODDR DDR_IO
DDR_WE O
–
–
–
–
–
–
–
– O, LOW
C15 VDDIODDR DDR_IO
DDR_BA0 O
–
–
–
–
–
–
–
– O, LOW
D14 VDDIODDR DDR_IO
DDR_BA1 O
–
–
–
–
–
–
–
– O, LOW
G13 VDDIODDR DDR_IO
DDR_BA2 O
–
–
–
–
–
–
–
– O, LOW
C19 VDDIODDR Reference DDR_CALN I
–
–
–
–
–
–
–
–
I
B19 GNDIODDR Reference DDR_CALP I
–
–
–
–
–
–
–
–
I
K12 VDDIODDR/2 Reference DDR_VREF I
–
–
–
–
–
–
–
–
I
W11 VBG
VBG
VBG
I
–
–
–
–
–
–
–
–
I
R12 VDDANA Reference ADCVREF I
–
–
–
–
–
–
–
–
I
W16 VDDUTMII USBHS
HHSDPC I/O
–
–
–
–
–
–
–
–
O, PD
V16 VDDUTMII USBHS
HHSDMC I/O
–
–
–
–
–
–
–
–
O, PD
W15 VDDUTMII USBHS
HHSDPB I/O
–
–
–
–
–
–
–
–
O, PD
V15 VDDUTMII USBHS
HHSDMB I/O
–
–
–
–
–
–
–
–
O, PD
W14 VDDUTMII USBHS
HHSDPA I/O DHSDP I/O
–
–
–
–
–
–
O, PD
16 SAMA5D4 Series [DATASHEET]
Atmel-11238C-ATARM-SAMA5D4-Datasheet_12-Jul-16