AD8114-EVAL 데이터 시트보기 (PDF) - Analog Devices
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AD8114-EVAL Datasheet PDF : 32 Pages
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AD8114/AD8115
Table 6. Operation Truth Table
CE UPDATE CLK DATA IN
1X
XX
01
f
Datai
01
00
f
D0…D4,
A0… A3
XX
XX
XX
DATA OUT
X
Datai-80
RESET
X
1
SER/
PAR
X
0
NA in parallel mode 1
1
X
1
X
X
0
X
Operation/Comment
No change in logic.
The data on the serial DATA IN line is loaded into
serial register. The first bit clocked into the serial register
appears at DATA OUT 80 clocks later.
The data on the parallel data lines, D0 to D4, are
loaded into the 80 bit serial shift register location
addressed by A0 to A3.
Data in the 80-bit shift register transfers into the
parallel latches that control the switch array.
Latches are transparent.
Asynchronous operation. All outputs are disabled.
Remainder of logic is unchanged.
D0
PARALLEL D1
DATA D2
(OUTPUT
ENABLE)
D3
D4
SER/PAR
DATA IN
(SERIAL)
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0
CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
S
D1
Q DQ
D0 CLK
DATA
OUT
CLK
CE
UPDATE
OUT0 EN
OUT1 EN
OUT2 EN
OUT3 EN
A0
OUT4 EN
A1
OUT5 EN
A2
OUT6 EN
A3
OUT7 EN
OUT8 EN
OUT9 EN
OUT10 EN
OUT11 EN
OUT12 EN
OUT13 EN
OUT14 EN
OUT15 EN
RESET
(OUTPUT ENABLE)
LE D
OUT0
B0
Q
LE D
OUT0
B1
Q
LE D
OUT0
B2
Q
LE D
OUT0
B3
Q
LE D
OUT0
EN
CLR Q
LE D
OUT1
B0
Q
LE D
OUT14
EN
CLR Q
LE D
OUT15
B0
Q
LE D
OUT15
B1
Q
LE D
OUT15
B2
Q
LE D
OUT15
B3
Q
LE D
OUT15
EN
CLR Q
DECODE
256
SWITCH MATRIX
Figure 4. Logic Diagram
16
OUTPUT ENABLE
Rev. B | Page 7 of 32
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