NXP Semiconductors
74HC175; 74HCT175
Quad D-type flip-flop with reset; positive-edge trigger
5. Pinning information
5.1 Pinning
+&
+&7
05
4
4
'
'
4
4
*1'
9&&
4
4
'
'
4
4
&3
DDD
Fig 4. Pin configuration DIP16
+&
+&7
05
4
4
'
'
4
4
*1'
9&&
4
4
'
'
4
4
&3
DDD
Fig 5. Pin configuration SO16
+&
+&7
05
4
4
'
'
4
4
*1'
9&&
4
4
'
'
4
4
&3
DDD
Fig 6. Pin configuration SSOP16
and TSSOP16
5.2 Pin description
Table 2. Pin description
Symbol
Pin
MR
1
Q0 to Q3
2, 7, 10, 15
Q0 to Q3
3, 6, 11, 14
D0 to D3
4, 5, 12, 13
GND
8
CP
9
VCC
16
Description
asynchronous master reset input (active LOW)
flip-flop output
complementary flip-flop output
data input
ground (0 V)
clock input (LOW-to-HIGH edge-triggered)
positive supply voltage
74HC_HCT175
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 4 — 8 April 2014
© NXP Semiconductors N.V. 2014. All rights reserved.
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