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4. Functional diagram
$
<
2(
$
2(
$
<
<
2(
$
2(
<
PQD
Fig 1. Logic symbol
Q$
Q2(
Fig 3. Logic diagram (one buffer/line driver)
5. Pinning information
5.1 Pinning
+&
+&7
2(
$
<
2(
$
<
*1'
9&&
2(
$
<
2(
$
<
DDD
Fig 4. Pin configuration for SOT108-1
74HC126; 74HCT126
Quad buffer/line driver; 3-state
(1
PQD
Fig 2. IEC logic symbol
Q<
PQD
+&
+&7
2(
$
<
2(
$
<
*1'
9&&
2(
$
<
2(
$
<
DDD
Fig 5. Pin configuration for SOT337-1 and SOT402-1
74HC_HCT126
Product data sheet
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Rev. 4 — 1 December 2015
© Nexperia B.V. 2017. All rights reserved
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