ADAS1000-1BCPZ(RevA) 데이터 시트보기 (PDF) - Analog Devices

부품명

상세내역

제조사

ADAS1000-1BCPZ
(Rev.:RevA)

Low Power, Five Electrode Electrocardiogram (ECG) Analog Front End

Analog Devices 

ADAS1000/ADAS1000-1/ADAS1000-2

Data Sheet

ADAS1000

LQFP LFCSP

14

2

4

12

5

11

6

10

62

16

ADAS1000-1

LFCSP

2

ADAS1000-2

LQFP LFCSP

10

6

11

5

12

4

13

3

14

2

60

18

3

13

22

52

52

19

55

55

21

53

53

20

54

54

61

17

17

9

7

7

8

7

27, 28

8

9

47, 46

29

45

41

35

44

32

43

33

53

25

45

31

42

34

8

9

47, 46

45

35

32

33

25

31

34

54

24

24

52

26

26

36

40

40

37

39

39

38

38

38

39

37

37

19

55

21

53

9

7

8

8

7

9

41

35

44

32

43

33

53

25

45

31

42

34

54

24

52

26

Mnemonic

ECG5_V2

ECG1

ECG2

ECG3

ECG4

ECG5

EXT_RESP_RA

EXT_RESP_LL

EXT_RESP_LA

RESPDAC_LL

SHIELD/

RESPDAC_LA

RESPDAC_RA

CM_OUT/WCT

CM_IN

RLD_SJ

RLD_OUT

CAL_DAC_IO

REFIN

REFOUT

REFGND

XTAL1, XTAL2

CLK_IO

CS

SCLK

SDI

PD

SDO

DRDY

RESET

SYNC_GANG

GPIO0/MCS

GPIO1/MSCLK

GPIO2/MSDO

GPIO3

Description

Analog Input, Chest Electrode 2 or Auxiliary Biopotential Input (V2).

Analog Input 1.

Analog Input 2.

Analog Input 3.

Analog Input 4.

Analog Input 5.

Optional External Respiration Input.

Optional External Respiration Input.

Optional External Respiration Input.

Optional path for higher performance respiration resolution, respiration

DAC drive, Negative Side 0.

Shared Pin (User-Configured).

Output of Shield Driver (SHIELD).

Optional Path for Higher Performance Respiration Resolution, Respiration

DAC Drive, Negative Side 1 (RESPDAC_LA).

Optional Path for Higher Performance Respiration Resolution, Respiration

DAC Drive, Positive Side.

Common-Mode Output Voltage (Average of Selected Electrodes). Not

intended to drive current.

Common-Mode Input.

Summing Junction for Right Leg Drive Amplifier.

Output and Feedback Junction for Right Leg Drive Amplifier.

Calibration DAC Input/Output. Output for a master device, input for a

slave. Not intended to drive current.

Reference Input. For standalone mode, use REFOUT connected to REFIN.

External 10 μF with ESR < 0.2 Ω in parallel with 0.1 μF bypass capacitors to

GND are required and should be placed as close to the pin as possible. An

external reference can be connected to REFIN.

Reference Output.

Reference Ground. Connect to a clean ground.

External crystal connects between these two pins; external clock drive

should be applied to CLK_IO. Each XTAL pin requires 15 pF to ground.

Buffered Clock Input/Output. Output for a master device; input for a slave.

Powers up in high impedance.

Chip Select and Frame Sync, Active Low. CS can be used to frame each

word or to frame the entire suite of data in framing mode.

Clock Input. Data is clocked into the shift register on a rising edge and

clocked out on a falling edge.

Serial Data Input.

Power-Down, Active Low.

Serial Data Output. This pin is used for reading back register configuration

data and for the data frames.

Digital Output. This pin indicates that conversion data is ready to be read

back when low, busy when high. When reading packet data, the entire

packet must be read to allow DRDY to return high.

Digital Input. This pin has an internal pull-up. This pin resets all internal

nodes to their power-on reset values.

Digital Input/Output (Output on Master, Input on Slave). Used for

synchronization control where multiple devices are connected together.

Powers up in high impedance.

General-Purpose I/O or Master 128 kHz SPI CS.

General-Purpose I/O or Master 128 kHz SPI SCLK.

General-Purpose I/O or Master 128 kHz SPI SDO.

General-Purpose I/O.

Rev. A | Page 16 of 80

Share Link: