74LVC573A 데이터 시트보기 (PDF) - NXP Semiconductors.
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74LVC573A
NXP Semiconductors.
74LVC573A Datasheet PDF : 20 Pages
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NXP Semiconductors
74LVC573A
Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state
5. Pinning information
5.1 Pinning
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
573
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
001aad099
Fig 5. Pin configuration for SO20 and (T)SSOP20
terminal 1
index area
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
573
GND(1)
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
001aad100
Transparent top view
(1) This is not a supply pin. The substrate is attached to this
pad using conductive die attach material. There is no
electrical or mechanical requirement to solder this pad.
However, if it is soldered, the solder land should remain
floating or be connected to GND.
Fig 6. Pin configuration for DHVQFN20 and
DHXQFN20
5.2 Pin description
Table 2.
Symbol
OE
LE
D[0:7]
Q[0:7]
GND
VCC
Pin description
Pin
1
11
2, 3, 4, 5, 6, 7, 8, 9
19, 18, 17, 16, 15, 14, 13, 12
10
20
Description
output enable input (active LOW)
latch enable input (active HIGH)
data input
data output
ground (0 V)
supply voltage
74LVC573A
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 5 — 19 February 2013
© NXP B.V. 2013. All rights reserved.
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