MC74HC160A 데이터 시트보기 (PDF) - ON Semiconductor
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MC74HC160A Datasheet PDF : 12 Pages
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MC74HC160A
FUNCTION DESCRIPTION
The HC160A is a programmable 4−bit synchronous
counters that feature parallel Load, synchronous or
asynchronous Reset, a Carry Output for cascading, and
count−enable controls. The HC160A is a BCD counter with
asynchronous Reset.
INPUTS
Clock (Pin 2)
The internal flip−flops toggle and the output count
advances with the rising edge of the Clock input. In addition,
control functions, such as loading occur with the rising edge
of the Clock input.
Preset Data Inputs P0, P1, P2, P3 (Pins 3, 4, 5, 6)
These are the data inputs for programmable counting.
Data on these pins may be synchronously loaded into the
internal flip−flops and appear at the counter outputs. P0 (pin
3) is the least−significant bit and P3 (pin 6) is the
most−significant bit.
OUTPUTS
Q0, Q1, Q2, Q3 (Pins 14, 13, 12, 11)
These are the counter outputs (BCD or binary). Q0 (pin
14) is the least−significant bit and Q3 (pin 11) is the
most−significant bit.
Ripple Carry Out (Pin 15)
When the counter is in its maximum state (1001 for the
BCD counters or 1111 for the binary counters), this output
goes high, providing an external look−ahead carry pulse that
may be used to enable successive cascaded counters. Ripple
Carry Out remains high only during the maximum count
state. The logic equation for this output is:
Ripple Carry Out =
Enable T Q0 Q1 Q2 Q3
for BCD counters
CONTROL FUNCTIONS
Resetting
A low level on the Reset pin (pin 1) resets the internal
flip−flops and sets the outputs (Q0 through Q3) to a low
level. The HC160A resets asynchronously.
Loading
With the rising edge of the Clock, a low level on Load (pin
9) loads the data from the Preset Data Input pins (P0, P1, P2,
P3) into the internal flip−flops and onto the output pins, Q0
through Q3. The count function is disabled as long as Load
is low.
Although the HC160A is a BCD counters, they may be
programmed to any state. If they are loaded with a state
disallowed in BCD code, they will return to their normal
count sequence within two clock pulses (see the Output State
Diagram).
Count Enable/Disable
These devices have two count−enable control pins:
Enable P (pin 7) and Enable T (pin 10). The devices count
when these two pins and the Load pin are high. The logic
equation is:
Count Enable = Enable P Enable T Load
The count is either enabled or disabled by the control
inputs according to Table 1. In general, Enable P is a
count−enable control; Enable T is both a count−enable and
a Ripple−Carry Output control.
Table 1. COUNT ENABLE/DISABLE
Control Inputs
Result at Outputs
Load Enable P Enable T Q0 − Q3 Ripple Carry Out
H
H
L
H
H
Count High when
Q0 −Q3 are max-
H
No Count imum*
X
L
H
No Count High when
Q0 −Q3 are max-
imum*
X
X
L
No Count
L
*Q0 through Q3 are maximum for the HC160A when Q3 Q2 Q1 Q0
= 1001.
0
1
2
3
4
15
5
14
6
13
7
12
11
10
9
8
Figure 2. Output State Diagrams HC160A BCD Counters
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