MTV512MV 데이터 시트보기 (PDF) - Myson Century Inc

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MTV512MV

8051 Embedded Monitor Controller 64K Flash Type

Myson Century Inc 

MTV512M

Preliminary

VSYNC Interrupt

The MTV512M checks the VSYNC input pulse and generates an interrupt at its leading edge. The VSYNC flag

is set each time when MTV512M detects a VSYNC pulse. The flag is cleared by S/W writing a “0”.

INTFLG F48h(r/w)

INTEN F49h(w)

Vsync

EVsync

INTFLG(w): Interrupt flag. An interrupt event will set its individual flag, and, if the corresponding interrupt enable

bit is set, the INT1 source of 8051 core will be driven by a zero level. Software MUST clear this

register while serving the interrupt routine.

Vsync = 1 → No action.

= 0 → Clears VSYNC interrupt flag.

INTFLG(r): Interrupt flag.

Vsync = 1 → Indicates a VSYNC interrupt.

INTEN(w): Interrupt enable.

EVsync = 1 → Enables VSYNC interrupt.

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