MAX8772 데이터 시트보기 (PDF) - Maxim Integrated

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MAX8772

Dual-Phase, QuickPWM Controller for IMVP-6+ CPU Core Power Supplies

Maxim Integrated 

CONFIDENTIAL INFORMATION – RESTRICTED TO INTEL® IMVP-6 LICENSEES

MAX8770/MAX8771/MAX8772 Dual-Phase, Quick-

PWM Controller for IMVP-6+ CPU Core Power Supplies

ELECTRICAL CHARACTERISTICS (continued)

(Circuit of Figure 1. VDD = VCC = VSHDN = VPSI = VDPRSTP = 5V, DPRSLPVR = GNDS = PGND_ = GND, VFB = VCCI = VCSP_ = VCSN_ =

1.200V, D0–D6 set for 1.20V (D0-D6 = 0001100). TA = -40°C to +105°C, unless otherwise specified. Typical values are at TA = +25°C.)

(Note 4)

PARAMETER

FAULT PROTECTION

Output Overvoltage Protection

Threshold

(MAX8770/MAX8771 Only)

Output Undervoltage Protection

Threshold

SYMBOL

CONDITIONS

MIN TYP MAX UNITS

VOVP

VUVP

Measured at FB with respect to unloaded

output voltage, rising edge,

PWM mode, or skip mode after output

reaches the regulation voltage

Measured at FB,

rising edge

Skip mode and

output have not

reached the

regulation voltage

Measured at FB with respect to unloaded

output voltage

250

1.75

-450

350

mV

1.85

V

-350

mV

CLKEN Startup Delay (Boot Time

Period)

Measured from the time when FB reaches

tBOOT the boot target voltage based on the slew

20

rate set by RTIME

100

µs

PWRGD, PHASEGD Startup

Delay

tPWRGD

Measured at startup from the time when

CLKEN goes low

3

8

ms

CLKEN, PWRGD Threshold

Measured at FB

with respect to

unloaded output

voltage

15mV hysteresis

(typ)

Lower threshold,

falling edge

(undervoltage)

Upper threshold,

rising edge

(overvoltage)

-350

+150

-250

mV

+250

PHASEGD Window Comparator

Thresholds

CLKEN, PWRGD, PHASEGD

Output Low Voltage

V(CCI,FB),

Lower threshold,

0.4V ≤ V(FB) ≤ 1.5V 0.6VFB nominal

-20

15mV hysteresis Upper threshold,

-20

(typ)

1.4VFB nominal

ISINK = 3mA

VRHOT Trip Threshold

VRHOT Output On-Resistance

VHOT

Measured at THRM, with respect to VCC,

falling edge, 115mV hysteresis (typ)

29.5

RVRHOT Low state

VCC Undervoltage Lockout

Threshold

VUVLO(VCC)

Rising edge, 50mV hysteresis, DL_ pulled

low below this level

4.1

DROOP AND BALANCE

DC Droop Amplifier Offset

-1.5

DC Droop Amplifier

Transconductance

∆IFB/(Σ∆VCS),

Gm(FB) VFB = VCSN_ = 1.2V,

580

VCSP_ - VCSN_ = 0 to +60mV

Current-Balance

Preamplifier Offsets

[V(CSPI, CSN_) - V(CPS2, CSN_)]

-1.5

at ICCI = 0

+20

mV

+20

0.4

V

30.5

%

11

Ω

4.45

V

+1.5

mV

620

µs

+1.5

mV

8 _______________________________________________________________________________________

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