MSC8126TMP6400(2007) 데이터 시트보기 (PDF) - Freescale Semiconductor
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MSC8126TMP6400 Datasheet PDF : 48 Pages
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Electrical Characteristics
The UPM machine and GPCM machine outputs change on the internal tick selected by the memory controller
configuration. The AC timing specifications are relative to the internal tick. SDRAM machine outputs change only
on the REFCLK rising edge.
Table 14. AC Timing for SIU Inputs
Value for Bus Speed in MHz
No.
Characteristic
Ref = CLKIN
Ref =
CLKOUT
Units
133
166
133
10 Hold time for all signals after the 50% level of the REFCLK rising edge
0.5
0.5
0.5
ns
11a ARTRY/ABB set-up time before the 50% level of the REFCLK rising
3.0
3.0
3.0
ns
edge
11b DBG/DBB/BG/BR/TC set-up time before the 50% level of the
REFCLK rising edge
3.3
3.3
3.3
ns
11c AACK set-up time before the 50% level of the REFCLK rising edge
2.9
2.9
2.9
ns
11d TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK
rising edge
• Data-pipeline mode
3.4
3.4
3.4
ns
• Non-pipeline mode
4.0
4.0
4.0
ns
12 Data bus set-up time before REFCLK rising edge in Normal mode
• Data-pipeline mode
1.8
1.7
1.8
ns
• Non-pipeline mode
4.0
4.0
4.0
ns
131 Data bus set-up time before the 50% level of the REFCLK rising edge
in ECC and PARITY modes
• Data-pipeline mode
2.0
2.0
2.0
ns
• Non-pipeline mode
7.3
7.3
7.3
ns
141 DP set-up time before the 50% level of the REFCLK rising edge
• Data-pipeline mode
2.0
2.0
2.0
ns
• Non-pipeline mode
6.1
6.1
6.1
ns
15a TS and Address bus set-up time before the 50% level of the REFCLK
rising edge
• Extra cycle mode (SIUBCR[EXDD] = 0)
3.6
3.6
3.8
ns
• No extra cycle mode (SIUBCR[EXDD] = 1)
5.0
5.0
5.0
ns
15b Address attributes: TT/TBST/TSZ/GBL set-up time before the 50%
level of the REFCLK rising edge
• Extra cycle mode (SIUBCR[EXDD] = 0)
3.5
3.5
3.5
ns
• No extra cycle mode (SIUBCR[EXDD] = 1)
4.4
4.4
4.4
ns
16 PUPMWAIT signal set-up time before the 50% level of the REFCLK
3.7
3.7
3.7
ns
rising edge
17 IRQx setup time before the 50% level; of the REFCLK rising edge3
4.0
4.0
4.0
ns
18 IRQx minimum pulse width3
6.0 + TREFCLK 6.0 + TREFCLK 6.0 + TREFCLK
ns
Notes: 1. Timings specifications 13 and 14 in non-pipeline mode are more restrictive than MSC8102 timings.
2. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.
3. Guaranteed by design
MSC8126 Quad Digital Signal Processor Data Sheet, Rev. 13
Freescale Semiconductor
23
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