MT89L85AP 데이터 시트보기 (PDF) - Zarlink Semiconductor Inc
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MT89L85AP Datasheet PDF : 25 Pages
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CMOS ST-BUSTM Family
MT89L85
Enhanced Digital Switch
Data Sheet
Features
• 3.3 volt supply
• 5 V tolerant inputs and TTL compatible outputs
• 256 x 256 channel non-blocking switch
• Programmable frame integrity for wideband
channels
• Automatic identification of ST-BUS/GCI interface
backplanes
• Per channel tristate control
• Patented message mode
• Non-multiplexed microprocessor interface
• Available in PLCC-44 and SSOP-48 packages
• Pin compatible with MT8985 device
• Low power consumption
Applications
• Medium size digital switch matrices
• Hyperchannel switching (e.g., ISDN H0)
• ST-BUS/MVIP™ interface functions
• Serial bus control and monitoring
• Centralized voice processing systems
• Data multiplexer
February 2006
Ordering Information
MT89L85AP 44 Pin PLCC
Tubes
MT89L85AN 48 Pin SSOP Tubes
MT89L85APR 44 Pin PLCC
Tape & Reel
MT89L85ANR 48 Pin SSOP Tape & Reel
MT89L85AN1 48 Pin SSOP* Tubes
MT89L85ANR1 48 Pin SSOP* Tape & Reel
MT89L85AP1 44 Pin PLCC* Tubes
MT89L85APR1 44 Pin PLCC* Tape & Reel
*Pb Free Matte Tin
-40°C to +85°C
Description
The MT89L85 Enhanced Digital Switch device is an
upgraded 3-volt version of the MT8985 Digital Switch.
It is pin compatible with the MT8985 and retains all of
the MT8985's functionality. The enhanced digital
switch is designed for switching PCM-encoded voice or
data, under microprocessor control, in digital
exchanges, PBXs and any ST-BUS/MVIP
environment. It provides simultaneous connections for
up to 256 64 kb/s channels. Each of the eight serial
inputs and outputs consist of 32 64 kbit/s channels
multiplexed to form a 2048 kbit/s stream. As the main
function in switching applications, the device provides
per-channel selection between variable or constant
throughput delays. The constant throughput delay
feature allows grouped channels such as ISDN H0 to
be switched through the device maintaining its
sequence integrity. The MT89L85 is ideal for medium
sized mixed voice/data switch and voice processing
applications.
**
C4i F0i RESET VDD VSS
ODE
STi0
STi1
STi2
STi3
STi4
STi5
STi6
STi7
Serial
to
Parallel
Converter
Data
Memory
Frame
Counter
Control Register
Control Interface
Output
MUX
Connection
Memory
Parallel
to
Serial
Converter
STo0
STo1
STo2
STo3
STo4
STo5
STo6
STo7
** for 48-pin SSOP only
DS CS R/W A5/ DTA D7/
A0
D0
CSTo
Figure 1 - Functional Block Diagram
1
Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 1999-2006, Zarlink Semiconductor Inc. All Rights Reserved.
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