IDT7007L15J 데이터 시트보기 (PDF) - Integrated Device Technology

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IDT7007L15J

HIGH-SPEED 32K x 8 DUAL-PORT STATIC RAM

Integrated Device Technology 

IDT7007S/L

High-Speed 32K x 8 Dual-Port Static RAM

Waveform of Read Cycles(5)

ADDR

CE

tRC

tAA(4)

tACE(4)

tAOE (4)

OE

Military, Industrial and Commercial Temperature Ranges

R/W

DATAOUT

tLZ (1)

tOH

VALID DATA(4)

tHZ (2)

BUSYOUT

tBDD (3,4)

2940 drw 07

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first CE or OE.

3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.

5. SEM = VIH.

Timing of Power-Up Power-Down

CE

tPU

ICC

50%

ISB

tPD

50%

,

2940 drw 08

9

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