P4C1256L-55SMB 데이터 시트보기 (PDF) - Semiconductor Corporation

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P4C1256L-55SMB

HIGH SPEED 32K x 8 STATIC CMOS RAM

Semiconductor Corporation 

TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CE CONTROLLED)(10)

P4C1256

Notes:

10. CE and WE must be LOW for WRITE cycle.

11. OE is LOW for this WRITE cycle to show tWZ and tOW.

12. If CE goes HIGH simultaneously with WE HIGH, the output remains

in a high impedance state

13. Write Cycle Time is measured from the last valid address to the first

transitioning address.

Document # SRAM119 REV G

Page 7 of 17

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