ADP3020 데이터 시트보기 (PDF) - Analog Devices

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ADP3020

High-Efficiency Notebook Computer Power Supply Controller

Analog Devices 

ADP3020

4. If critical signal lines (including the voltage and current sense

lines of the ADP3020) must cross through power circuitry,

it is best if a signal ground plane can be interposed between

those signal lines and the traces of the power circuitry. This

serves as a shield to minimize noise injection into the sig-

nals at the expense of making signal ground a bit noisier.

5. The PGND pin of the ADP3020 should connect first to a

ceramic bypass capacitor on the VIN pin, and then into the

power ground plane using the shortest possible trace. How-

ever, the power ground plane should not extend under other

signal components, including the ADP3020 itself. If neces-

sary, follow the preceding guideline to use the signal plane as

a shield between the power ground plane and the signal

circuitry.

6. The AGND pin of the ADP3020 should connect first to the

REF capacitor, and then into the signal ground plane. In cases

where no signal ground plane can be used, short interconnec-

tions to other signal ground circuitry in the power converter

should be used.

7. The output capacitors of the power converter should be

connected to the signal ground plane even though power

current flows in the ground of these capacitors. For this

reason, it is advised to avoid critical ground connections

(e.g., the signal circuitry of the power converter) in the signal

ground plane between the input and output capacitors. It

is also advised to keep the planar interconnection path short

(i.e., have input and output capacitors close together).

8. The output capacitors should also be connected as closely

as possible to the load (or connector) that receives the power.

If the load is distributed, the capacitors should also be dis-

tributed, and generally in proportion to where the load tends

to be more dynamic.

9. Absolutely avoid crossing any signal lines over the switching

power path loop, described below.

Power Circuitry

10. The switching power path should be routed on the PCB to

encompass the smallest possible area in order to minimize

radiated switching noise energy (i.e., EMI). Failure to take

proper precaution often results in EMI problems for the

entire PC system as well as noise-related operational prob-

lems in the power converter control circuitry. The switching

power path is the loop formed by the current path through

the input capacitors, the two FETs (and the power Schottky

diode if used), including all interconnecting PCB traces and

planes. The use of short and wide interconnection traces

is especially critical in this path for two reasons: it mini-

mizes the inductance in the switching loop, which can cause

high-energy ringing, and it accommodates the high current

demand with minimal voltage loss.

11. A power Schottky diode (1 ~ 2 A dc rating) placed from the

lower FET’s source (anode) to drain (cathode) will help to

minimize switching power dissipation in the upper FET. In

the absence of an effective Schottky diode, this dissipation

occurs through the following sequence of switching events.

The lower FET turns off in advance of the upper FET turning

on (necessary to prevent cross-conduction). The circulating

current in the power converter, no longer finding a path for

current through the channel of the lower FET, draws cur-

rent through the inherent body-drain diode of the FET.

The upper FET turns on, and the reverse recovery char-

acteristic of the lower FET’s body-drain diode prevents the

drain voltage from being pulled high quickly.

The upper FET then conducts very large current while it

momentarily has a high voltage forced across it, which trans-

lates into added power dissipation in the upper FET. The

Schottky diode minimizes this problem by carrying a majority

of the circulating current when the lower FET is turned off,

and by virtue of its essentially nonexistent reverse recov-

ery time.

12. Whenever a power-dissipating component (e.g., a power

MOSFET) is soldered to a PCB, the liberal use of vias,

both directly on the mounting pad and immediately sur-

rounding it, is recommended. Two important reasons for

this are: improved current rating through the vias (if it is

a current path), and improved thermal performance, espe-

cially if the vias are extended to the opposite side of the

PCB where a plane can more readily transfer the heat to

the air.

13. The output power path, though not as critical as the switch-

ing power path, should also be routed to encompass a small

area. The output power path is formed by the current path

through the inductor, the output capacitors, and back to the

input capacitors.

14. For best EMI containment, the power ground plane should

extend fully under all the power components except the

output capacitors. These are: the input capacitors, the power

MOSFETs and Schottky diode, the inductor, and any snub-

bing elements that might be added to dampen ringing. Avoid

extending the power ground under any other circuitry or

signal lines, including the voltage and current sense lines.

Signal Circuitry

15. The CS and SW traces should be Kelvin-connected to the

upper MOSFET drain and source so that the additional

voltage drop due to current flow on the PCB at the current

sense comparator connections does not affect the sensed

voltage. It is desirable to have the ADP3020 close to the out-

put capacitor bank and not in the output power path, so that

any voltage drop between the output capacitors and the

AGND pin is minimized, and voltage regulation is not

compromised.

REV. 0

–21–

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