TMC22091KHC 데이터 시트보기 (PDF) - Cadeka Microcircuits LLC.
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TMC22091KHC Datasheet PDF : 60 Pages
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PRODUCT SPECIFICATION
TMC22091/TMC22191
Pin Descriptions (continued)
Pin Name
CS
Pin Number
84-Lead 100-Lead
PLCC MQFP
6
72
Value
TTL
R/W
RESET
7
73
TTL
5
71
TTL
Video Output
COMPOSITE
33
LUMA
35
CHROMA
37
Analog Interface
VREF
30
COMP
39
RREF
31
2
1 V P-P
5
1 V P-P
8
1 V P-P
98 +1.23 V
10
0.1 µF
99
392Ω
JTAG Test Interface
TDI
25
TMS
24
93
TTL
92
TTL
TCK
23
91
TDO
22
90
Power Supply
VDD
27, 64, 81 41, 62, 95
VDDA
40-43 13-17
DGND
10, 26, 65, 42, 61, 76,
80
94
AGND
32, 34, 36, 4, 6, 9,
38
100
TTL
TTL
+5 V
+5 V
0.0 V
0.0 V
Pin Function Description
Chip Select. When CS is HIGH, the microprocessor interface
port, D7-0, is set to HIGH impedance and ignored. When CS is
LOW, the microprocessor can read or write parameters over
D7-0. One additional falling edge of CS is needed to move input
data to its assigned working registers.
Bus Read/Write Control. When R/W and CS are LOW, the
microprocessor can write to the control registers or CLUT over
D7-0. When R/W is HIGH and CS is LOW, it can read the
contents of any CLUT address or control register over D7-0.
Master Reset Input. Bringing RESET LOW sets the software
reset control bit, SRESET, LOW, forcing the internal state
machines to their starting states and disabling all outputs.
Bringing RESET HIGH synchronizes the internal pixel clock
(PCK = PXCK / 2) to maintain a defined pipeline delay through
the TMC22x91. If HRESET is set HIGH, the encoder is enabled
when RESET goes HIGH. If HRESET is LOW, the host restarts
the TMC22x91 by setting SRESET HIGH. RESET does not
affect the CLUT or the control registers, except SRESET.
NTSC/PAL Video. Analog output of composite D/A converter,
nominally 1.35 volt peak-to-peak into a 37.5Ω load.
Luminance-only Video. Analog output of luminance D/A
converter, nominally 1.35 volt peak-to-peak into a 37.5Ω load.
Chrominance-only Video. Analog output of chrominance D/A
converter, nominally 1.35 volt peak-to-peak into a 37.5Ω load.
Voltage Reference Input. External voltage reference input,
internal voltage reference output, nominally 1.235 V.
Compensation Capacitor. Connection point for 0.1µf
decoupling capacitor.
Current-setting Resistor. Connection point for external
current-setting resistor for D/A converters. The resistor (392Ω)
is connected between RREF and AGND. Output video levels
are inversely proportional to the value of RREF.
Data Input Port. Boundary scan data input port.
Scan Select Input. Boundary scan (HIGH)/normal operation
(LOW) selector.
Scan Clock Input. Boundary scan clock.
Data Output Port. Boundary scan data output port.
Positive digital power supply.
Positive analog power supply.
Digital Ground.
Analog Ground.
9
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