NXP Semiconductors
PH9030L
N-channel TrenchMOS logic level FET
3
VGS(th)
(V)
2
1.5
1
0.5
0
-60
max
typ
min
003aab272
0
60
120
180
Tj (°C)
Fig 7. Gate-source threshold voltage as a
function of junction temperature
2
a
1.6
003aab467
1.2
0.8
0.4
0
−60
0
60
120
180
Tj (°C)
25
RDSon
(mΩ)
20
15
10
5
0
0
VGS (V) = 3.2 3.4
003aab733
4.5
5
10
20
40
60
80
ID (A)
Fig 8. Drain-source on-state resistance as a
function of drain current; typical values
VDS
ID
VGS(pl)
VGS(th)
VGS
QGS1 QGS2
QGS
QGD
QG(tot)
003aaa508
Fig 10. Gate charge waveform definitions
Fig 9. Normalized drain-source on-state
resistance factor as a function of junction
temperature
PH9030L_1
Product data sheet
Rev. 01 — 29 July 2008
© NXP B.V. 2008. All rights reserved.
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