MH32D72AKLA-75 데이터 시트보기 (PDF) - MITSUBISHI ELECTRIC

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MH32D72AKLA-75

2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

MITSUBISHI ELECTRIC  

Preliminary Spec.

Some contents are subject to change without notice.

MITSUBISHI LSIs

MH32D72AKLA-10,-75

2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module

[Asynchronous S ELF REFRESH]

Asynchronous Self -refresh mode is entered by CKE=L within 2 tCLK after issuing a REFA command

(/CS=/RAS=/CAS=L,/WE=H). Once the self-refresh is initiated, it is maintained as long as CKE is kept

low. During the self-refresh mode, CKE is asynchronous and the only enable input, all other inputs

including CLK are disabled and ignored, so that power consumption due to synchronous inputs is saved.

To exit the self-refresh, supplying stable CLK inputs, asserting DESEL or NOP command and then

asserting CKE for longer than tXSNR/tXSRD.

/CLK

CLK

/CS

/RAS

/CAS

/WE

CKE

A0-12

BA0,1

Asynchronous Self-Refresh

max 2 tCLK

tXSNR

Act

Self Refresh Exit

MIT-DS-0398-1.1

MITSUBISHI ELECTRIC

24.Nov.2000

33

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