Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MH32D64AKQJ-75,-10
2,147,483,684-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
COM M AND TRUTH TABLE
COMMAND
CKE CKE
MNEMONIC n-1 n
/S
A10 A0-9,
/RAS /CAS /WE BA0,1
note
/AP 11
Deselect
No Operation
Row Address Entry &
Bank Activate
Single Bank Precharge
Precharge All Banks
Column Address Entry
& Write
Column Address Entry
& Write with
Auto-Precharge
Column Address Entry
& Read
DESEL
NOP
ACT
PRE
PREA
WRIT E
WRITEA
READ
H
X
H
X
X
X
X
X
X
H
X
L
H
H
H
X
X
X
H
H
L
L
H
H
V
V
V
H
H
L
L
H
L
V
L
X
H
H
L
L
H
L
X
H
X
H
H
L
H
L
L
V
L
V
H
H
L
H
L
L
V
H
V
H
H
L
H
L
H
V
L
V
Column Address Entry
& Read with
Auto-Precharge
Auto-Refresh
Self-Refresh Entry
READA
REFA
REFS
Self-Refresh Exit
REFSX
Burst Terminate
Mode Register Set
TERM
MRS
H
H
L
H
L
H
V
H
V
H
H
L
L
L
H
X
X
X
H
L
L
L
L
H
X
X
X
L
H
H
X
X
X
X
X
X
L
H
L
H
H
H
X
X
X
H
H
L
H
H
L
X
X
X1
H
H
L
L
L
L
L
L
V2
H=High Level, L=Low Level, V=Valid, X=Don't Care, n=CLK cycle number
NOTE:
1. Applies only to read bursts with autoprecharge disabled; this command is undefined (and should
not be used) for read bursts with autoprecharge enabled, and for write bursts.
2. BA0-BA1 select either the Base or the Extended Mode Register (BA0 = 0, BA1 = 0 selects Mode
Register; BA0 = 1, BA1 = 0 selects Extended Mode Register; other combinations of BA0-BA1 are
reserved; A0-A11 provide the op-code to be written to the selected Mode Register.
MIT-DS-0422-0.0
MITSUBISHI
ELECTRIC
17.May.2001
6