TDA7580(2002) 데이터 시트보기 (PDF) - STMicroelectronics
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TDA7580 Datasheet PDF : 31 Pages
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TDA7580
SAI INTERFACE
Figure 3. SAI Timings
SDI0-1
LRCKR
SCKR
(RCKP=0)
Valid
Valid
tlrs
tdt
tsdis
tsckpl
tlrh
tsdih
tsckph
tsckr
Timing
Description
TDSP Internal DSP Clock Period (Typical 1/74.1MHz)
tsckr
Minimum Clock Cycle
tdt
SCKR active edge to data out valid
tlrs
LRCK setup time
tlrh
LRCK hold time
tsdid
SDI setup time
tsdih
SDI hold time
tsckph Minimum SCK high time
tsckpl
Minimum SCK low time
Note TDSP = DSP master clock cycle time = 1/FDSP
Figure 4. SAI protocol when RLRS=0; RREL=0; RCKP=1; RDIR=0
LRCKR
SCKR
LEFT
RIGHT
Value
13.495
32*TDSP
40
16
9
16
9
0.5*tsckr
0.5*tsckr
SDI0-1
LSB(n-1)
MSB(n)
MSB-1(n)
MSB-2(n)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
16/31
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