C8051F131 데이터 시트보기 (PDF) - Silicon Laboratories

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C8051F131

Mixed Signal ISP Flash MCU Family

Silicon Laboratories 

C8051F120/1/2/3/4/5/6/7

C8051F130/1/2/3

Table 18.1.Port I/O DC Electrical Characteristics .................................................. 239

19. System Management Bus / I2C Bus (SMBus0) ................................................. 261

Table 19.1.SMB0STA Status Codes and States ................................................... 274

20. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 277

Table 20.1.SPI Slave Timing Parameters ............................................................. 290

21. UART0 ................................................................................................................... 291

Table 21.1.UART0 Modes ..................................................................................... 292

Table 21.2.Oscillator Frequencies for Standard Baud Rates ................................ 299

22. UART1 ................................................................................................................... 303

Table 22.1.Timer Settings for Standard Baud Rates Using The Internal Oscillator ....

310

Table 22.2.Timer Settings for Standard Baud Rates Using an External Oscillator 310

Table 22.3.Timer Settings for Standard Baud Rates Using an External Oscillator 311

Table 22.4.Timer Settings for Standard Baud Rates Using the PLL ..................... 311

Table 22.5.Timer Settings for Standard Baud Rates Using the PLL ..................... 312

23. Timers ................................................................................................................... 313

24. Programmable Counter Array ............................................................................ 331

Table 24.1.PCA Timebase Input Options .............................................................. 332

Table 24.2.PCA0CPM Register Settings for PCA Capture/Compare Modules ..... 333

25. JTAG (IEEE 1149.1) ............................................................................................. 345

Table 25.1.Boundary Data Register Bit Definitions ............................................... 346

26. Document Change List ....................................................................................... 353

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Rev. 1.3

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