ADT7411ARQZ10 데이터 시트보기 (PDF) - Analog Devices

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ADT7411ARQZ10

SPI®/I2C® Compatible, 10-Bit Digital Temperature Sensor and 8-Channel ADC

Analog Devices 

ADT7411

Serial Interface Selection

The CS line controls the selection between I2C and SPI.

Figure 16 shows the selection process necessary to lock the SPI

interface mode.

To communicate to the ADT7411 using the SPI protocol, send

three pulses down the CS line as shown in Figure 33. On the

third rising edge (marked as C in Figure 33), the part selects and

locks the SPI interface. Communication to the device is now

limited to the SPI protocol.

As per most SPI standards, the CS line must be low during

every SPI communication to the ADT7411, and high at all other

times. Typical examples of how to connect the dual interface as

I2C or SPI are shown in Figure 31 and Figure 32.

ADT7411

VDD

VDD

10kΩ

10kΩ

CS

SDA

SCL

I2C ADDRESS = 1001 000

ADD

Figure 31. Typical I2C Interface Connection

ADT7411

LOCK AND

SELECT SPI

CS

DIN

SCLK

DOUT

VDD

820Ω 820Ω 820Ω

SPI FRAMING

EDGE

Figure 32. Typical SPI Interface Connection

The following sections describe in detail how to use the I2C and

SPI protocols associated with the ADT7411.

I2C Serial Interface

Like all I2C compatible devices, the ADT7411 has a 7-bit serial

address. The four MSBs of this address for the ADT7411 are set

to 1001. The three LSBs are set by Pin 11, ADD. The ADD pin

can be configured three ways to give three different address

options: low, floating, and high. Setting the ADD pin low gives a

serial bus address of 1001 000, leaving it floating gives the

Address 1001 010, and setting it high gives the Address 1001

011. The recommended pull-up resistor value is 10 kΩ.

There is an enable/disable bit for the SMBus timeout. When this

is enabled, the SMBus will timeout after 25 ms of no activity. To

enable it, set Bit 6 of the Control Configuration 2 register. The

power-up default is with the SMBus timeout disabled.

The ADT7411 supports SMBus packet error checking (PEC)

and its use is optional. It is triggered by supplying the extra

clocks for the PEC byte. The PEC is calculated using CRC-8.

The frame clock sequence (FCS) conforms to CRC-8 by the

polynomial

C(x) = x8 + x2 + x1 + 1

Consult the SMBus specification (www.smbus.org) for more

information.

The serial bus protocol operates as follows:

1. The master initiates a data transfer by establishing a start

condition, defined as a high-to-low transition on the serial

data line SDA while the serial clock line SCL remains high.

This indicates that an address/data stream will follow. All

slave peripherals connected to the serial bus respond to the

start condition and shift in the next eight bits, consisting of

a 7-bit address (MSB first) plus an R/W bit, which deter-

mines the direction of the data transfer, i.e., whether data

will be written to or read from the slave device.

The peripheral whose address corresponds to the trans-

mitted address responds by pulling the data line low during

the low period before the ninth clock pulse, known as the

acknowledge bit. All other devices on the bus now remain

idle while the selected device waits for data to be read from

or written to it. If the R/W bit is 0, the master will write to

the slave device. If the R/W bit is 1, the master will read

from the slave device.

2. Data is sent over the serial bus in sequences of nine clock

pulses: eight bits of data followed by an acknowledge bit

from the receiver of data. Transitions on the data line must

occur during the low period of the clock signal and remain

stable during the high period, because a low-to-high trans-

ition when the clock is high may be interpreted as a stop

signal.

3. When all data bytes have been read or written, stop con-

ditions are established. In write mode, the master will pull

the data line high during the 10th clock pulse to assert a

stop condition. In read mode, the master device will pull

the data line high during the low period before the ninth

clock pulse. This is known as No Acknowledge. The master

will then take the data line low during the low period

before the 10th clock pulse, and then high during the 10th

clock pulse to assert a stop condition.

Any number of bytes of data can be transferred over the

serial bus in one operation, but it is not possible to mix

read and write in one operation. This is because the type of

operation is determined at the beginning and cannot sub-

sequently be changed without starting a new operation.

Rev. A | Page 28 of 36

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