ADT7411ARQZ10 데이터 시트보기 (PDF) - Analog Devices

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ADT7411ARQZ10

SPI®/I2C® Compatible, 10-Bit Digital Temperature Sensor and 8-Channel ADC

Analog Devices 

ADT7411

Table 35.

Bit Function

D0 0 = Enable internal THIGH interrupt.

1 = Disable internal THIGH interrupt.

D1 0 = Enable internal TLOW interrupt.

1 = Disable internal TLOW interrupt.

D2 0 = Enable external THIGH interrupt or AIN1 interrupt.

1 = Disable external THIGH interrupt or AIN1 interrupt.

D3 0 = Enable external TLOW interrupt.

1 = Disable external TLOW interrupt.

D4 0 = Enable external temperature fault interrupt.

1 = Disable external temperature fault interrupt.

D5 0 = Enable AIN2 interrupt.

1 = Disable AIN2 interrupt.

D6 0 = Enable AIN3 interrupt.

1 = Disable AIN3 interrupt.

D7 0 = Enable AIN4 interrupt.

1 = Disable AIN4 interrupt.

Interrupt Mask 2 Register (Read/Write) [Address = 1Eh]

This mask register is an 8-bit read/write register that can be

used to mask out any interrupts that can cause the INT/INT pin

to go active.

Table 36. Interrupt Mask 2

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up.

Table 37.

Bit

D0

D1

D2

D3

D4

D5:D7

Function

0 = Enable AIN5 interrupt.

1 = Disable AIN5 interrupt.

0 = Enable AIN6 interrupt.

1 = Disable AIN6 interrupt.

0 = Enable AIN7 interrupt.

1 = Disable AIN7 interrupt.

0 = Enable AIN8 interrupt.

1 = Disable AIN8 interrupt.

0 = Enable VDD interrupts.

1 = Disable VDD interrupts.

Reserved. Only write 0s.

Internal Temperature Offset Register (Read/Write)

[Address = 1Fh]

This register contains the offset value for the internal

temperature channel. A twos complement number can be

written to this register, which is then added to the measured

result before it is stored or compared to limits. In this way, a sort

of one-point calibration can be done whereby the whole

transfer function of the channel can be moved up or down.

From a software point of view this may be a very simple method

to vary the characteristics of the measurement channel if the

thermal characteristics change. Because it is an 8-bit register, the

temperature resolution is 1°C.

Table 38. Internal Temperature Offset

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up.

External Temperature Offset Register (Read/Write)

[Address = 20h]

This register contains the offset value for the external tempera-

ture channel. A twos complement number can be written to this

register, which is then added to the measured result before it is

stored or compared to limits. In this way, a sort of one-point

calibration can be done whereby the whole transfer function of

the channel can be moved up or down. From a software point of

view, this may be a very simple method to vary the character-

istics of the measurement channel if the thermal characteristics

change. Because it is an 8-bit register, the temperature resolution

is 1°C.

Table 39. External Temperature Offset

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

0* 0* 0* 0* 0* 0* 0* 0*

*Default settings at power-up

VDD VHIGH Limit Register (Read/Write) [Address = 23h]

This limit register is an 8-bit read/write register that stores the

VDD upper limit that will cause an interrupt and activate the

INT/INT output (if enabled). For this to happen, the measured

VDD value has to be greater than the value in this register. The

default value is 5.46 V.

Table 40. VDD VHIGH Limit

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

1* 1* 0* 0* 0* 1* 1* 1*

*Default settings at power-up.

VDD VLOW Limit Register (Read/Write) [Address = 24h]

This limit register is an 8-bit read/write register that stores the

VDD lower limit that will cause an interrupt and activate the

INT/INT output (if enabled). For this to happen, the measured

VDD value has to be less than or equal to the value in this regis-

ter. The default value is 2.7 V.

Table 41. VDD VLOW Limit

D7 D6 D5 D4 D3 D2 D1 D0

D7 D6 D5 D4 D3 D2 D1 D0

0* 1* 1* 0* 0* 0* 1* 0*

*Default settings at power-up.

Rev. A | Page 24 of 36

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